5P49V5935 datasheet, PDF - EEWORLD Datasheet

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5P49V5935: DescriptionGenerates up to four independent output frequencies; File Size421KB，33 Pages; ManufacturerIDT (Integrated Device Technology, Inc.); Websitehttp://www.idt.com/

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5P49V5935 Overview

Generates up to four independent output frequencies

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Programmable Clock Generator

5P49V5935

PRELIMINARY DATASHEET

Description

The 5P49V5935 is a programmable clock generator intended

for high performance consumer, networking, industrial,

computing, and data-communications applications.

Configurations may be stored in on-chip One-Time

Programmable (OTP) memory or changed using I

interface. This is IDTs fifth generation of programmable clock

technology (VersaClock

5).

The 5P49V5935 by default uses an integrated 25MHz crystal

as input reference. It also has a redundant external clock

input. A glitchless manual switchover functions allows

selection of either one as mentioned above as input reference

during normal operation.

Two select pins allow up to 4 different configurations to be

programmed and accessible using processor GPIOs or

bootstrapping. The different selections may be used for

different operating modes (full function, partial function, partial

power-down), regional standards (US, Japan, Europe) or

system production margin testing.

The device may be configured to use one of two I

addresses to allow multiple devices to be used in a system.

Features

•

Generates up to four independent output frequencies

•

High performance, low phase noise PLL, <0.7 ps RMS

typical phase jitter on outputs:

– PCIe Gen1, 2, 3 compliant clock capability

– USB 3.0 compliant clock capability

– 1 GbE and 10 GbE

•

Four fractional output dividers (FODs)

•

Independent Spread Spectrum capability on each output

pair

•

Four banks of internal non-volatile in-system

programmable or factory programmable OTP memory

•

C serial programming interface

•

One reference LVCMOS output clock

•

Four universal output pairs:

– Each configurable as one differential output pair or two

LVCMOS outputs

I/O Standards:

– Single-ended I/Os: 1.8V to 3.3V LVCMOS

– Differential I/Os - LVPECL, LVDS and HCSL

•

Pin Assignment

OUT0_SEL_I2CB

•

Input frequency ranges:

– LVDS, LVPECL, HCSL Differential Clock Input (CLKIN,

CLKINB) – 1MHz to 350MHz

Output frequency ranges:

– LVCMOS Clock Outputs – 1MHz to 200MHz

– LVDS, LVPECL, HCSL Differential Clock Outputs –

1MHz to 350MHz

•

OUT1B

DDO

OUT1

DDD

CLKIN

CLKINB

DDA

CLKSEL

24 23 22 21 20 19

•

Individually selectable output voltage (1.8V, 2.5V, 3.3V) for

DDO

OUT2

OUT2B

DDO

OUT3

OUT3B

each output pair

EPAD

10 11 12

SEL1/SDA

SEL0/SCL

OUT4B

•

Redundant clock inputs with manual switchover

Programmable loop bandwidth

Programmable output to output skew

Programmable slew rate control

Individual output enable/disable

Power-down mode

1.8V, 2.5V or 3.3V core V

DDD

, V

DDA

Available in 24-pin VFQFPN 4mm x 4mm package

-40° to +85°C industrial temperature operation

SD/OE

24-pin VFQFPN

5P49V5935 REVISION B 07/13/15

DDO

OUT4

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