MACH 5 CPLD Family
I
MAC ncludes
Adva H 5A F
a
nce
Info mily
rma
tion
Fifth Generation MACH Architecture
FEATURES
x
High logic densities and I/Os for increased logic integration
x
x
x
x
x
x
x
— 128 to 512 macrocell densities
— 68 to 256 I/Os
Wide selection of density and I/O combinations to support most application needs
— 6 macrocell density options
— 8 I/O options
— Up to 5 I/O options per macrocell density
— Up to 6 density & I/O options for each package
Performance features to fit system needs
— 5.5 ns t
PD
Commercial, 7.5 ns t
PD
Industrial
— 182 MHz f
CNT
— Four programmable power/speed settings per block
Flexible architecture facilitates logic design
— Multiple levels of switch matrices allow for performance-based routing
— 100% routability and pin-out retention
— Synchronous and asynchronous clocking, including dual-edge clocking
— Asynchronous product- or sum-term set or reset
— 16 to 64 output enables
— Functions of up to 32 product terms
Advanced capabilities for easy system integration
— 3.3-V & 5-V JEDEC-compliant operations
— JTAG (IEEE 1149.1) compliant for boundary scan testing
— 3.3-V & 5-V JTAG in-system programming
— PCI compliant (-5/-6/-7/-10/-12 speed grades)
— Safe for mixed supply voltage system design
— Programmable pull-up or Bus-Friendly™ Inputs & I/Os
— Individual output slew rate control
— Hot socketing
— Programmable security bit
Advanced EE CMOS process provides high performance, cost effective solutions
Supported by Vantis DesignDirect™ software for rapid logic development
— Supports HDL design methodologies with results optimized for Vantis
— Flexibility to adapt to user requirements
— Software partnerships that ensure customer success
Vantis and Third-party hardware programming support
— Lattice/VantisPRO™ (formerly known as MACHPRO
®
) software for in-system programmability
support on PCs and Automated Test Equipment
— Programming support on all major programmers including Data I/O, BP Microsystems, Advin,
and System General
Publication#
20446
Amendment/0
Rev:
G
Issue Date:
November 1998
Table 1. MACH 5 Device Features
1
Feature
Supply Voltage (V)
Macrocells
Maximum User I/O Pins
t
PD
(ns)
t
SS
(ns)
t
COS
(ns)
f
CNT
(MHz)
Static Power (mA)
JTAG-Compliant
PCI-Compliant
M5-128
M5LV-128
5
128
120
7.5
4.0
6.0
125
35
Yes
Yes
3.3
128
120
5.5
3.0
4.5
182
35
Yes
Yes
M5-192
5
192
160
7.5
4.0
6.0
125
45
Yes
Yes
M5-256
M5LV-256
5
256
160
7.5
4.0
6.0
125
55
Yes
Yes
3.3
256
160
5.5
3.0
4.5
182
55
Yes
Yes
M5-320
M5LV-320
5
320
192
7.5
4.0
6.0
125
70
Yes
Yes
3.3
320
192
7.5
4.0
6.0
125
70
Yes
Yes
M5-384
M5LV-384
5
384
192
7.5
4.0
6.0
125
75
Yes
Yes
3.3
384
192
7.5
4.0
6.0
125
75
Yes
Yes
M5-512
M5LV-512
5
512
256
7.5
4.0
6.0
125
100
Yes
Yes
3.3
512
256
7.5
4.0
6.0
125
100
Yes
Yes
Note:
1. “M5-xxx” is for 5-V devices. “M5LV-xxx” is for 3.3-V devices.
Table 2. MACH 5A Device Features
1 ,2
Feature
Supply Voltage (V)
Macrocells
Maximum User I/O Pins
t
PD
(ns)
t
SS
(ns)
t
COS
(ns)
f
CNT
(MHz)
Static Power (mA)
JTAG-Compliant
PCI-Compliant
M5A3-128
M5A5-128
3.3
128
120
5.5
3.0
4.5
182
TBD
Yes
Yes
5
128
120
5.5
3.0
4.5
182
TBD
Yes
Yes
M5A3-192
M5A5-192
3.3
192
120
5.5
3.0
4.5
182
TBD
Yes
Yes
5
192
120
5.5
3.0
4.5
182
TBD
Yes
Yes
M5A3-256
M5A5-256
3.3
256
160
5.5
3.0
4.5
182
TBD
Yes
Yes
5
256
160
5.5
3.0
4.5
182
TBD
Yes
Yes
M5A3-320 M5A3-384 M5A3-512
3.3
320
192
5.5
3.0
4.5
182
TBD
Yes
Yes
3.3
384
192
5.5
3.0
4.5
182
TBD
Yes
Yes
3.3
512
256
5.5
3.0
4.5
182
TBD
Yes
Yes
Notes:
1. All information on MACH 5A devices is Advance Information. Please contact a Vantis sales representative for details on
availability.
2. “M5A5-xxx” is for 5-V devices “M5A3-xxx” is for 3.3-V devices.
GENERAL DESCRIPTION
The MACH
®
5 family consists of a broad range of high-density and high-I/O Complex
Programmable Logic Devices (CPLDs). The fifth-generation MACH architecture yields fast speeds
at high CPLD densities, low power, and supports additional features such as in-system
programmability, JTAG testability, and advanced clocking options (Tables 1 and 2). Both the
MACH 5 and the MACH 5A families offer 5-V (M5-xxx and M5A5-xxx) and 3.3-V (M5LV-xxx and
M5A3-xxx) operation.
Manufactured in state-of-the-art ISO 9000 qualified fabrication facilities on EECMOS process
technologies, MACH 5 devices are available with pin-to-pin delays as fast as 5.5 ns (Tables 3 and
4). The 5.5, 6.5, 7.5, 10, and 12-ns devices are compliant with the
PCI Local Bus Specification
.
2
MACH 5 Family
Table 3. MACH 5 Speed Grades
Speed Grade
1
Device
M5-128
M5LV-128
M5-192
M5-256
M5LV-256
M5-320
M5LV-320
M5-384
M5LV-384
M5-512
M5LV-512
Note:
1. C = Commercial grade, I = Industrial grade
C
C
-5
-7
C
C,I
C
C
C, I
C
C
C
C
C
C
-10
C, I
C, I
C, I
C, I
C, I
C, I
C, I
C, I
C, I
C, I
C, I
-12
C, I
C, I
C, I
C, I
C, I
C, I
C, I
C, I
C, I
C, I
C, I
-15
C, I
I
C, I
C, I
I
C, I
C, I
C, I
C, I
C, I
C, I
I
I
I
I
I
I
I
I
-20
I
Table 4. MACH 5A Speed Grades
Speed Grade
1
Device
M5A3-128
M5A5-128
M5A3-192
M5A5-192
M5A3-256
M5A5-256
M5A3-320
M5A3-384
M5A3-512
-5
C
C
C
C
C
C
C (Note 2)
C (Note 2)
C (Note 2)
C (Note 2)
C (Note 2)
-6
-7
C, I
C, I
C, I
C, I
C, I
C, I
C, I (Note 2)
C, I (Note 2)
C, I (Note 2)
-10
C, I
C, I
C, I
C, I
C, I
C, I
C, I
C, I
C, I
-12
C, I
C, I
C, I
C, I
C, I
C, I
C, I
C, I
C, I
-15
I
I
I
I
I
I
I
I
I
Notes:
1. C = Commercial grade, I = Industrial grade. All information on MACH 5A devices is Advance Information. Please contact a
Vantis sales representative for details on availability.
2. The –5 and –6 commercial and –7 industrial speed grades are under development for M5A3-320, M5A3-384, and M5A3-512.
Please contact a Vantis sales representative for details on availability.
With Vantis’ unique hierarchical architecture, the MACH 5 family provides densities up to 512
macrocells to support full system logic integration. Extensive routing resources ensure pinout
retention as well as high utilization. It is ideal for PAL
®
block device integration and a wide range
of other applications including high-speed computing, low-power applications, communications,
and embedded control. At each macrocell density point, Vantis offers several I/O and package
options to meet a wide range of design needs (Tables 5 and 6).
MACH 5 Family
3
Table 5. MACH 5 Package and I/O Options
1
Package
100-pin TQFP
100-pin PQFP
144-pin TQFP
144-pin PQFP
160-pin PQFP
208-pin PQFP
240-pin PQFP
256-ball BGA
352-ball BGA
Note:
1. The I/O options indicated with a “*” are only available for the “LV” devices.
M5-128
M5LV-128
68, 74*
68
104*
104
120
104
120
160
M5-192
68
68
M5-256
M5LV-256
68, 74*
68
104*
104
120
160
120
160
184
192
120
160
184
192
120
160
184
192
256
M5-320
M5LV-320
M5-384
M5LV-384
M5-512
M5LV-512
Table 6. MACH 5A Package and I/O Options
1
Package
100-pin PQFP
100-pin TQFP
144-pin TQFP
160-pin PQFP
208-pin PQFP
256-ball BGA
352-ball BGA
M5A3-128
M5A5-128
68
74
104
120
M5A3-192
M5A5-192
68
74
104
120
M5A3-256
M5A5-256
68
74
104
120
160
120
160
192
120
160
192
120
160
192
256
M5A3-320
M5A3-384
M5A3-512
Note:
1. All information on MACH 5A devices is Advance Information. Please contact a Vantis sales representative for details on
availability.
Advanced power management options allow designers to incrementally reduce power while
maintaining the level of performance needed for today’s complex designs. I/O safety features
allow for mixed-voltage design, and both the 3.3-V and the 5-V device versions are in-system
programmable through a JTAG-compliant interface.
Vantis offers software design support for MACH devices in both the MACHXL
®
and DesignDirect
development systems. The DesignDirect development system is the Vantis implementation
software that includes support for all Vantis CPLD, FPGA and SPLD devices. This system is
supported under Windows ’95, ’98 and NT as well as Sun Solaris and HPUX.
DesignDirect software is designed for use with design entry, simulation and verification software
from leading-edge tool vendors such as Cadence, Exemplar Logic, Mentor Graphics, Model
Technology, Synopsys, Synplicity, Viewlogic and others. It accepts EDIF 2 0 0 input netlists,
generates JEDEC files for Vantis PLDs and creates industry standard EDIF, Verilog, VITAL compliant
VHDL and SDF simulation netlists for design verification.
DesignDirect software is also available in product configurations that include VHDL and Verilog
synthesis from Exemplar Logic and VHDL, Verilog RTL and gate level timing simulation from Model
Technology. Schematic capture and ABEL entry, as well as functional simulation, are also provided.
4
MACH 5 Family
FUNCTIONAL DESCRIPTION
The MACH 5 architecture consists of PAL blocks connected by two levels of interconnect. The
block
interconnect
provides routing among 4 PAL blocks. This grouping of PAL blocks joined by the
block interconnect is called a
segment
. The second level of interconnect, the
segment
interconnect
, ties all of the segments together. The only logic difference between any two MACH
5 devices is the number of segments. Therefore, once a designer is familiar with one device,
consistent performance can be expected across the entire family. All devices have four clock pins
available which can also be used as logic inputs.
Block:
16 MCs
CLK
4
Segment Interconnect
20446G-001
Figure 1. MACH 5 Block Diagram
The MACH 5 PAL blocks consist of the elements listed below (Figure 2). While each PAL block
resembles an independent PAL device, it has superior control and logic generation capabilities.
x
I/O cells
x
Product-term array and Logic Allocator
x
Macrocells
x
Register control generator
x
Output enable generator
I/O Cells
The I/Os associated with each PAL block have a path directly back to that PAL block called
local
feedback
. If the I/O is used in another PAL block, the
interconnect feeder
assigns a
block
interconnect
line to that signal. The interconnect feeder acts as an input switch matrix. The block
and segment interconnects provide connections between any two signals in a device. The
block
feeder
assigns block interconnect lines and local feedback lines to the PAL block inputs.
MACH 5 Family
Block Interconnect
Segment:
4 Blocks
5
京公网安备 11010802033920号
EEWORLD
