BU-65552, BU-65551 and BU-65550
MIL-STD-1553 BC/RT/MT
INTERFACE CARD
DESCRIPTION
The BU-65552, BU-65551 and
BU-65550 provide full, intelligent
interfacing between a dual redundant
MIL-STD-1553 Data Bus and a PCM-
CIA socket. Software controls these
cards operation as either a 1553 Bus
Controller (BC), Remote Terminal
(RT), or Bus Monitor (MT). The BU-
65552, BU-65551 and BU-65550 are
packaged in a Type II PCMCIA PC
Card. The BU-65552 is designed
around the Mini-ACE Plus, which has
backward compatability to the BU-
61586 and provides 64k x 16 on-
board shared RAM. Using the sup-
plied drivers and libraries, this card
will require only 32k bytes of PC
memory. The The BU-65552, BU-
65551 and BU-65550 feature DDC's
BU-61586 Advanced Communication
Engine (ACE). As such, it includes
dual
transceiver
and
encoder/decoder, complete 1553 pro-
tocol, shared RAM and memory man-
agement logic for all three modes.
On-board Interrupt Mask and
Interrupt Status Registers support
flexible operation for both interrupt
and polling applications. The memory
management scheme for RT mode
provides an option for separation of
broadcast data plus a circular buffer
option for individual RT subaddresses
to offload the host CPU.The PCMCIA
interface includes 256 bytes of
attribute memory as well as the four
standard PCMCIA card configuration
registers. Additional features include
a wrap-around Built-In-Test, and soft-
ware programmable RT address
selection. Free C Runtime Library and
comprehensive Menu Applications for
DOS, Windows 95/98 and Windows
NT. These cards support all dual
redundant mode codes and message
formats. Additionally, these cards
allow the use of commercial off-the-
shelf or ruggedized laptop and note-
book computers in applications
requiring a MIL-STD-1553 interface.
Full compliance with both MIL-STD-
1553 and PCMCIA 2.10 make the
BU-65552, BU-65551 and BU-65550
an excellent choice for real-time sim-
ulation, test, and system integration
applications.
FEATURES
• Type II PCMCIA 2.10 Compatible
PC Card
• MIL-STD-1553 Dual Redundant
BC\RT\MT with Simultaneous
RT/Monitor
• Multiprotocol Support of
MIL-STD-1553A and B Notice 2
• Flexible RT Data Buffering
• Selective Message Monitor
• 64K x 16 Shared RAM (BU-65552)
• 4K x 16 Shared RAM (BU-65551)
• 12K x 16 Shared RAM (BU-65550)
• Runtime Libraries for Windows 3.1,
Windows 95/98 and Windows NT
• Menu Software for Windows 3.1,
Windows 95/98 and Windows NT
68 PIN CARD
CONNECTOR SOCKET
CE1, CE2, WE/PGM, IORD,
IQWR, RESET, REG, OE
RDYB, SY/IREQ, INPACK,
WP/IOIS16, BVD1/STSCHG,
BVD2/SPKR, WAIT
PCMCIA
Interface
Adapter
BD15..BDØ
BU-61586
Card
Configuration
Registers
ACE
1553
BC/RT/MT
1553
BUS
D15..DØ
Attribute
Memory
A15..AØ
BU-65552 supplied with
DDC-70093-1 Interface Cable
BU-65551 supplied with
DDC-57613-1 Interface Cable
BU-65550 supplied with
DDC-57612-1 Interface Cable
VCC
GND
CD1, CD2
CLOCK
OSCILLATOR
FIGURE 1. BU-65552, BU-65551 AND BU-65550 BLOCK DIAGRAM
© 1994, 1999 Data Device Corporation
TABLE 1. BU-65552, BU-65551 AND BU-65550 SPECIFICATIONS
PARAMETER
ABSOLUTE MAXIMUM RATINGS
+5 V Supply Voltage
RECEIVER
Threshold Voltage, Transformer
Coupled, Measured on Stub
Common Mode Voltage
TRANSMITTER
Differential Output Voltage
!
Direct Coupled Across 35 ohms,
Measured on Bus
!
Transformer Coupled,
Measured on Stub
Output Noise, Differential
(Direct Coupled)
Output Offset Voltage,
Direct Coupled Across 35 ohms
Rise/Fall Time
POWER SUPPLY REQUIREMENTS
Voltages/Tolerances
!
+5V
Current Drain @ + 5.0 V
!
Idle
!
25% Transmitter Duty Cycle
!
50% Duty Cycle
!
100% Duty Cycle
POWER DISSIPATION
Total PC Card (V
cc
= +5.0 V)
!
Idle
!
25% Duty Cycle
!
50% Duty Cycle
!
100% Duty Cycle
1553 MESSAGE TIMING
RT Response Time
Completion of CPU Write
(BC Start-to Start of FIRST BC
Message)
BC Intermessage Gap
(See Note 1)
BC/RT/MT Response Timeout
(See Note 2)
!
18.5 nominal
!
22.5 nominal
!
50.5 nominal
!
128.0 nominal
Transmitter Watchdog Timeout
THERMAL
BU-65552
Operating Temperature
Storage Temperature
BU-65551
Operating Temperature
Storage Temperature
BU-65550
Operating Temperature
Storage Temperature
Vibration
Shock
Operating Humidity
Non-operating Humidity
4
2.5
MIN
-0.3
0.200
TYP
MAX
7.0
0.860
10
UNITS
V
V
P
-
P
V
PEAK
TABLE 1. BU-65552, BU-65551 AND BU-65550 SPECIFICATIONS
(continued)
PARAMETER
PHYSICAL CHARACTERISTICS
Size
Weight
MIN
TYP
MAX
UNITS
in
(mm)
oz
(gm)
3.370 x 2.126 x 0.197
(85.6 x 54.0 x 5.0)
2.8
(80)
6
18
7
20
9
27
10
V
P
-
P
V
P
-
P
mV
P
-
P
,
diff
mV
nsec
Notes:
(1) Typical value for minimum intermessage gap time. Under software control,
may be lengthened to (65,535 ms minus message time), in increments of 1
µ
s.
(2) Software programmable (4 options). Includes RT-to-RT Timeout (Mid-Parity of
Transmit Command to Mid-Sync of Transmitting RT Status).
TABLE 2. HOST SYSTEM REQUIREMENTS
HARDWARE REQUIREMENTS
!
Socket Interface Compliant with PCMCIA Release 2.10 or higher
SOFTWARE REQUIREMENTS
!
Card Services Driver Compliant to PCMCIA Release 2.10 or higher
-90
100
90
300
FUNCTIONAL OVERVIEW
4.5
80
225
385
700
5.5
110
300
490
860
V
mA
mA
mA
mA
W
0.4
0.98
1.16
1.47
0.55
1.18
1.81
3.07
7
W
W
W
µsec
µsec
µsec
GENERAL
The BU-65552, BU-65551 and BU-65550 (See FIGURE 1) pro-
vides a user-friendly interface between the serial MIL-STD-1553
Bus and a PCMCIA interface socket. The operating modes of
these cards are controlled through the use of 24 on-board regis-
ters. 1553 message traffic is stored and retrieved using the ded-
icated, memory mapped, on-board 12K words of RAM. The var-
ious registers control and operate the BU-65552, BU-65551 and
BU-65550. They include the five Configuration Registers,
Start/Reset Register, Time Tag Register, Interrupt Mask
Register, and Interrupt Status Register. The Configuration
Registers define the operating mode and memory management
features. The Start/Reset Register provides various reset and
BC/MT start functions. The Interrupt Mask Register enables
desired interrupts, with the interrupt priority level being jumper
programmable by the user. The cause of interrupts may be
determined by a single READ operation, by means of the
Interrupt Status Register. The Time Tag Register features pro-
grammable resolution and is used to time tag messages in BC,
RT, or MT modes.
The BU-65552 64K x16 of static RAM is shared by the PC host
and the 1553 Bus with memory arbitration handled automatical-
ly by the BU-65552.
The BU-65551 4K x16 of static RAM is shared by the PC host
and the 1553 Bus with memory arbitration handled automatical-
ly by the BU-65551.
The BU-65550 12K x16 of static RAM is shared by the PC host
and the 1553 Bus with memory arbitration handled automatical-
ly by the BU-65550.
The BU-65552, BU-65551 and BU-65550 will withhold the WAIT
signal (assert to logic "0") to the PCMCIA socket interface while
a word is being transferred to or from the 1553 Bus. Since the
memory arbitration is handled by simply stretching the hand-
shake cycle, the wait state is transparent to the PC host proces-
sor's software. A maximum wait of 2.6
µ
s can occur
9.5
17.5
21.5
49.5
127
18.5
22.5
50.5
128
668
19.5
23.5
51.5
129
µsec
µsec
µsec
µsec
µsec
0
-20
-25
-55
55
65
70
80
°C
°C
°C
°C
0
55
°C
-20
65
°C
2
Random vibration, 0.1 g / Hz
from 20 Hz to 2000 Hz
40g, 11ms, half sine
0 to 95% non-condensing
100% condensing
2
In addition to storing the 1553 message data, the RAM imple-
ments the Stacks and Look-Up Tables required for the different
modes of operation. A global double buffering mechanism is
available to prevent partially updated information from being
transferred to or from the 1553 Bus. For RT mode, there is a pro-
grammable option to separate broadcast message data from
non-broadcast data. This provides compliance to MIL-STD-
1553. In addition, for RT mode, there is the choice of storing
either a single message, a double buffer data structure, or a cir-
cular buffer data structure. The size of the circular buffer is pro-
grammable up to 8192 words, on a Tx/Rx/Bcst-subaddress
basis.
The BU-65552, BU-65551 and BU-65550 support programma-
ble command illegalization for RT mode. This allows individual
Command Words to be illegalized as a function of
T / R
bit, sub-
address, and word count/mode code. Since the illegalization
scheme is RAM based, it is inherently self-testable.
A Descriptor Stack or Command Stack is maintained for BC, RT,
and MT modes. This records the status of each message, the
time the message was transmitted or received, and contains
either the received 1553 command and Data Block Pointer (in
RT or MT mode) or the actual address of the 1553 message
block (in BC mode). In RT mode, a Lookup Table is provided to
store the addresses of the data blocks to be used when receiv-
ing or transmitting messages for the individual subaddresses.
The PC Cards RT mode is multiprotocol, supporting MIL-STD-
1553A, MIL-STD-1553B Notice 2, STANAG 3838 (including
EFA bus), and the McAir A3818, A5232, and A5690 protocols.
The BU-65552, BU-65551 and BU-65550 implement three mon-
itor modes: a word monitor, a selective message monitor, and a
combined RT/selective message monitor.
PCMCIA INTERFACE
The BU-65552, BU-65551 and BU-65550 provide a Card
Information Structure (CIS) within the attribute memory space of
the PCMCIA interface. The CIS contains device configuration
information structures called basic compatibility tuples. The for-
mat of these configuration tuples is defined within the PCMCIA
interface standard. In addition to the CIS there are the four stan-
dard PCMCIA configuration registers (Configuration Option
Register, Card Configuration and Status Register, Pin
Replacement Register, and Socket and Copy Register).
The CIS, also referred to as the Metaformat, provides a level of
device information which allows a card resource manager or an
application program to identify and fully configure the card.
MEMORY MANAGEMENT
The BU-65552, BU-65551 and BU-65550 incorporate complete
memory management and processor interface logic. The soft-
ware interface to the host processor is implemented by means
of 24 on-board registers plus up to 64K words of RAM. For all
three modes, a stack area of RAM is maintained. In BC mode,
the stack allows for the scheduling of multimessage frames. For
all three modes, the stack provides a real-time chronology of all
messages processed. In addition to the stack processing, the
memory management logic performs storage, retrieval, and
manipulation functions involving pointer and message data
structures for all three modes.
The BU-65552, BU-65551 and BU-65550 provide a number of
programm-able options for RT mode memory management. In
compliance with MIL-STD-1553, received data from broadcast
messages may be optionally separated from nonbroadcast
received data. For each transmit, receive or broadcast subad-
dress, either a single-message data block or a variable-sized
(128 to 8192 words) circular buffer may be allocated for data
storage. In addition to helping ensure data consistency, the cir-
cular buffer feature provides a means of greatly reducing host
processor overhead for bulk data transfer applications. End-of-
message interrupts may be enabled either globally, following
error messages, on a Tx/Rx/Bcst-subaddress basis, or when any
particular Tx/Rx/Bcst-subaddress circular buffer reaches its
lower boundary.
INTERRUPTS
The BU-65552, BU-65551 and BU-65550 provide many pro-
grammable options for interrupt generation and handling. The
interrupt output pin (
INT
) has three software programmable
modes of operation: a pulse, a level output cleared under soft-
ware control, or a level output automatically cleared following a
read of the Interrupt Status Register.
Individual interrupts are enabled by the Interrupt Mask Register.
The host processor may easily determine the cause of the inter-
rupt by using the Interrupt Status Register. The Interrupt Status
Register provides the current state of the interrupt conditions.
The Interrupt Status Register may be updated in two ways. In the
standard interrupt handling mode, a particular bit in the Interrupt
Status Register will be updated only if the condition exists and
the corresponding bit in the Interrupt Mask Register is enabled.
In the enhanced interrupt handling mode, a particular bit in the
Interrupt Status Register will be updated if the condition exists
regardless of the contents of the corresponding Interrupt Mask
Register bit. In any case, the respective Interrupt Mask Register
bit enables an interrupt for a particular condition.
The BU-65552, BU-65551 and BU-65550 provide maskable
interrupts and 15-bit Interrupt Status Register for end of mes-
sage, end of BC message list, erroneous messages, Status Set
(BC mode), Time Tag Register Rollover, RT Address Parity Error
conditions, BC retry, data stack rollover, command stack
rollover, transmitter watchdog timeout, or RAM parity error. The
Interrupt Status Register allows the host processor to determine
the cause of all interrupts by means of a single READ operation.
INTERNAL COMMAND ILLEGALIZATION
The BU-65552, BU-65551 and BU-65550 implemen internal
command illegalization for RT mode. The illegalization architec-
ture allows for any subset of the 4096 possible combinations of
broadcast/own address,
T / R
bit, subaddress, and word
count/mode code to be illegalized. The illegalization scheme is
under software control of the host processor. As a result, it is
inherently self-testable.
3
INTERNAL TIME TAG
The BU-65552, BU-65551 and BU-65550 include an internal
read/writable Time Tag Register. This register is a CPU
read/writable 16-bit counter with a programmable resolution of
either 2, 4, 8, 16, 32, or 64
µ
s per LSB. Another option allows the
Time Tag Register to be incremented under software control.
This supports self-test for the Time Tag Register.
For each message processed, the value of the Time Tag regis-
ter is loaded into the second location of the respective descrip-
tor stack entry ("TIME TAG WORD") for both BC and RT modes.
Additional options are provided to clear the Time Tag Register
following a Synchronize (without data) mode command or load
the Time Tag Register following a Synchronize (with data) mode
command. Another option enables an interrupt request and a bit
in the Interrupt Status Register to be set when the Time Tag
Register rolls over from FFFF to 0000 (hex). Assuming the Time
Tag Register is not loaded or reset, this will occur at approxi-
mately 4-second time intervals, for 64
µ
s/LSB resolution, down
to 131 ms intervals, for 2
µ
s/LSB resolution.
Another programmable option for RT mode is for the Service
Request Status Word bit to be automatically cleared following
the PC Cards response to a Transmit Vector Word mode com-
mand.
TABLE 3. COMMON MEMORY ADDRESS MAPPING
HEX
ADDRESS
0000, 0001
0002, 0003
0004, 0005
0004, 0005
0006, 0007
0006, 0007
0008, 0009
000A, 000B
000C, 000D
000E, 000F
0010, 0011
0012, 0013
0014, 0015
0016, 0017
0018, 0019
001A,001B
001C, 001D
001E, 001F
0020, 0021
•
•
•
002E,002F
0030, 0031
•
•
•
7FFE, 7FFF
DESCRIPTION/ACCESSIBILITY
Interrupt Mask Register (RD/WR)
Configuration Register # 1 (RD/WR)
Configuration Register # 2 (RD/WR)
Configuration Register # 2 (RD/WR)
Start/Reset Register (WR)
BC/RT Command Stack Pointer Register (RD)
BC Control Word/RT Subaddress Control Word
Register (RD/WR)
Time Tag Register (RD/WR)
Interrupt Status Register (RD)
Configuration Register #3
Configuration Register #4
Configuration Register #5
Data Stack Address Register (RD/WR)
BC Frame Time Remaining Register (RD)*
BC Time Remaining to Next Message Register (RD)*
BC Frame Time*/RT Last Command/MT Trigger Word*
Register (RD/WR)
RT Status Word Register (RD)
RT BIT Word Register (RD)
Test Mode Register 0
•
•
•
Test Mode Register 7
reserved
•
•
•
reserved
ADDRESSING, INTERNAL REGISTERS, MEMORY
MANAGEMENT, AND INTERRUPTS
ADDRESSING THESE CARDS
All internal pointers used by these cards are assumed to be
word
addresses, however
byte
addressing is used by the PC to
access memory and registers in the card. For example, to
access the the Area A Stack Pointer at word offset address 0100
(hex), a byte address offset of 0200 (hex) must be used (i.e. the
byte address is determined by multiplying the word address by
two).
The shared RAM space starts at
byte
location 8000 if the mem-
ory allocation were contiguous. The registers are mapped into
memory locations 0X0000 through 0X002F. The memory
address space between 0X0030 and 0X7FFF is reserved. The
64K x 16 RAM uses page swapping, which is done in the device
driver.
COMMON MEMORY ADDRESS MAP
The software interface of the BU-65552, BU-65551 and BU-
65550 to the host processor consists of 17 internal operational
registers for normal operation, an additional 8 test registers, plus
shared memory (64K x 16 for BU-65552, 4K x 16 for BU-65551
and 12K x 16 for BU-65550). Both the registers and the shared
memory reside in the PCMCIA common memory space. See
TABLE 3. The BITMAPS of the 17 internal registers are shown
in TABLES 4 through 21.
Definition of the address mapping and accessibility for the BU-
65552, BU-65551 and BU-65550 17 nontest registers, and the
test registers, is as follows:
8000, 8001
12K x 16 Shared RAM (RD/WR) See NOTE below.
•
•
•
•
•
•
DFFE, DFFF 12K x 16 Shared RAM (RD/WR)
E000, E001
•
•
•
FFFE, FFFF
reserved
•
•
•
reserved
NOTES: 1. Normally RAM Addresses will be defined as an offset
from the base address
2. BU-65551 shared RAM is 4K x 16
Interrupt Mask Register:
Used to enable and disable interrupt
requests for various conditions.
Configuration Registers #1 and #2:
Used to select the PC
Cards mode of operation, and for software control of RT Status
Word bits, Active Memory Area, BC Stop-on-Error, RT Memory
Management mode selection, and control of the Time Tag oper-
ation.
4
Start/Reset Register:
Used for "command" type functions, such
as software reset, BC/MT Start, Interrupt Reset, Time Tag
Reset, and Time Tag Register Test. The Start/Reset Register
includes provisions for stopping the BC in its auto-repeat mode,
either at the end of the current message or at the end of the cur-
rent BC frame.
BC/RT Command Stack Pointer Register:
Allows the host
CPU to determine the pointer location for the current or most
recent message when the PC Card is in BC or RT mode.
BC Control Word/RT Subaddress Control Word Register:
In BC mode, allows host access to the current or most recent BC
Control Word. The BC Control Word contains bits that select the
active bus and message format, enable off-line self-test, mask-
ing of Status Word bits, enable retries and interrupts, and spec-
ify MIL-STD-1553A or -1553B error handling. In RT mode, this
register allows host access to the current or most recent
Subaddress Control Word. The Subaddress Control Word is
used to select the memory management scheme and enable
interrupts for the current message. The read/write accessibility
can be used as an aid for testing the ACE.
Time Tag Register:
Maintains the value of a real-time clock.
The resolution of this register is programmable from among 2, 4,
8, 16, 32, and 64
µ
s/LSB. The TAG_CLK input signal also may
cause an external oscillator to clock the Time Tag Register.
Start-of-Message (SOM) and End-of-Message (EOM)
sequences in BC, RT, and Message Monitor modes cause a
write of the current value of the Time Tag Register to the stack
area of RAM.
Interrupt Status Register:
Mirrors the Interrupt Mask Register
and contains a Master Interrupt bit. It allows the host processor
to determine the cause of an interrupt request by means of a sin-
gle READ operation.
Configuration Registers #3, #4, and #5:
Used to enable many
of the BU-65552, BU-65551 and BU-65550 advanced features.
These include all the enhanced mode features; that is, all the
functionality beyond that of the previous generation product, the
BUS-65529 that makes use of the Advanced Integrated Mux
Hybrid with Enhanced RT Features (AIM-HY'er). For all three
modes, use of the Enhanced Mode enables the various read-
only bits in Configuration Register #1.
For BC mode, the enhanced mode features include the expand-
ed BC Control Word and BC Block Status Word, additional Stop-
On-Error and Stop-On-Status Set functions, frame auto-repeat,
programmable intermessage gap times, automatic retries,
expanded Status Word Masking, and the capability to generate
interrupts following the completion of any selected message.
For RT mode, the enhanced mode features include the expand-
ed RT Block Status Word, the combined RT/Selective Message
Monitor mode, internal wrapping of the "
RTFAIL
" output signal
(from the J' chip)to the "
RTFLAG
" RT Status Word bit, the double
buffering scheme for individual receive (broadcast) subaddress-
es, and the alternate (fully software programmable) RT Status
Word.
For MT mode, use of the enhanced mode enables use of the
Selective Message Monitor, the combined RT/Selective Monitor
modes, and the monitor triggering capability.
Data Stack Address Register:
Used to point to the current
address location in shared RAM used for storing message words
(second Command Words, Data Words, RT Status Words) in the
Selective Word Monitor mode.
Frame Time Remaining Register:
Provides a read only indi-
cation of the time remaining in the current BC frame. The reso-
lution of this register is 100
µ
s/LSB.
Message Time Remaining Register:
Provides a read only indi-
cation of the time remaining before the start of the next message
in a BC frame. The resolution of this register is 1
µ
s/LSB.
BC Frame/RT Last Command/MT Trigger Word Register:
In BC mode, it programs the BC frame time for use in the frame
auto-repeat mode. The resolution of this register is 100
µ
s/LSB,
with a range of 6.55 seconds. In RT mode, this register stores
the current (or most previous) 1553 Command Word processed
by the ACE RT; in the Word Monitor mode, this register specifies
a 16-bit Trigger (Command) Word. The Trigger Word may be
used to start or stop the monitor, or to generate interrupts.
Status Word Register and BIT Word Registers:
Provide read-
only indications of the BU-65552, BU-65551 and BU-65550 RT
Status and BIT Words.
Test Mode Registers 0-7:
These registers may be used to facil-
itate built-in testing of the BU-65552, BU-65551 and BU-65550 .
5
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