IDT74LVC2952A
3.3V CMOS OCTAL BUS TRANSCEIVER AND REGISTER
EXTENDED COMMERCIAL TEMPERATURE RANGE
3.3V CMOS OCTAL BUS
TRANSCEIVER AND
REGISTER WITH 3-STATE OUT-
PUTS AND 5 VOLT TOLERANT I/O
FEATURES:
–
–
–
0.5 MICRON CMOS Technology
ESD > 2000V per MIL-STD-883, Method 3015;
> 200V using machine model (C = 200pF, R = 0)
1.27mm pitch SOIC, 0.65mm pitch SSOP,
0.635mm pitch QSOP, 0.65mm pitch TSSOP packages
Extended commercial range of – 40°C to +85°C
V
CC
= 3.3V ±0.3V, Normal Range
V
CC
= 2.3V to 3.6V, Extended Range
CMOS power levels (0.4µW typ. static)
Rail-to-Rail output swing for increased noise margin
All inputs, outputs and I/O are 5 Volt tolerant
Supports hot insertion
IDT74LVC2952A
DESCRIPTION:
The LVC2952A octal bus transceiver and register is built using ad-
vanced dual metal CMOS technology. This high speed low power device
is organized as 8-bit back-to-back registers with separate input and output
control for indepedent control of data flow in either direction. Data on the
A or B bus is stored in the registers on the low-to-high transition of the clock
(CLKAB or CLKBA) input, provided that the clock-enable (CLKENAB or
CLKENBA)
input is low. Taking the output-enable (OEAB or
OEBA)
input
low accesses the data of either port.
All pins can be driven from either 3.3V or 5V devices. This feature allows
the use of this device as a translator in a mixed 3.3V/5V system environ-
ment.
The LVC2952A has been designed with a
±
24mA output driver. This
driver is capable of driving a moderate to heavy load while maintaining
speed performance.
N
O
FO T
R
R E
N CO
EW M
M
D E
ES N
D
IG E
N D
S
–
–
–
–
–
–
–
Drive Feature for LVC2952A:
– Balanced Output Drivers:
±24mA
APPLICATIONS:
• 5V and 3.3V mixed voltage systems
• Data communication and telecommunication systems
FUNCTIONAL BLOCK DIAGRAM
CLKENAB
11
CLKAB
10
9
OEAB
CLKENBA
13
CLKBA
OEBA
14
15
C
1
A
1
16
1
D
8
B
1
C
1
1
D
TO SEVEN OTHER CHANNELS
EXTENDED COMMERCIAL TEMPERATURE RANGE
1
c
1999 Integrated Device Technology, Inc.
OCTOBER 1999
DSC-4581/-
IDT74LVC2952A
3.3V CMOS OCTAL BUS TRANSCEIVER AND REGISTER
EXTENDED COMMERCIAL TEMPERATURE RANGE
PIN CONFIGURATION
B
8
B
7
B
6
B
5
B
4
B
3
B
2
B
1
OEAB
CLKAB
CLKENAB
GND
1
2
3
4
5
6
7
8
9
10
11
12
SO24-2
SO24-7
SO24-8
SO24-9
ABSOLUTE MAXIMUM RATINGS
V
CC
A
8
A
7
A
6
A
5
A
4
A
3
A
2
A
1
OEBA
CLKBA
CLKENBA
Symbol
V
TERM
T
STG
I
OUT
I
IK
I
OK
I
CC
I
SS
Description
Terminal Voltage with Respect to GND
Storage Temperature
DC Output Current
Continuous Clamp Current,
V
I
< 0 or V
O
< 0
Continuous Current through
each V
CC
or GND
(1)
Unit
V
°C
mA
mA
mA
8LVC
24
23
22
21
20
19
18
17
16
15
14
13
Max.
– 0.5 to +6.5
– 65 to +150
– 50 to +50
– 50
±100
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or
any other conditions above those indicated in the operational sections
of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect reliability.
CAPACITANCE
(T
A
= +25°C, f = 1.0MH
Z
)
Symbol
C
IN
C
OUT
Parameter
(1)
Input Capacitance
Output
Capacitance
I/O Port
Capacitance
Conditions
V
IN
= 0V
V
OUT
= 0V
V
IN
= 0V
Typ.
4.5
5.5
6.5
Max.
6
8
8
Unit
pF
pF
pF
8LVC Link
SOIC/ SSOP/ QSOP/ TSSOP
TOP VIEW
C
I/O
NOTE:
1. As applicable to the device type.
PIN DESCRIPTION
Pin Names
OEAB
OEBA
CLKENAB
CLKENBA
CLKAB
CLKBA
Ax
BX
Description
A-to-B Output Enable Input (Active LOW)
B-to-A Output Enable Input (Active LOW)
A-to-B Clock Enable Input (Active LOW)
B-to-A Clock Enable Input (Active LOW)
A-to-B Clock Input
B-to-A Clock Input
A-to-B Data Inputs or B-to-A 3-State Outputs
B-to-A Data Inputs or A-to-B 3-State Outputs
FUNCTION TABLE
CLKENAB
H
X
L
L
X
Inputs
CLKAB
OEAB
X
H or L
↑
↑
X
L
L
L
L
H
(1, 2)
Outputs
Bx
B
0(3)
B
0(3)
L
H
Z
Ax
X
X
L
H
X
NOTES:
1. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
Z = High-Impedance
↑
= LOW-to-HIGH Transition
2. A-to-B data flow is shown; B-to-A flow control is similar but uses
CLKENBA,
CLKBA, and
OEBA.
3. B
0
= Level of B before the indicated steady-state input conditions
were established.
2
IDT74LVC2952A
3.3V CMOS OCTAL BUS TRANSCEIVER AND REGISTER
EXTENDED COMMERCIAL TEMPERATURE RANGE
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Operating Condition: T
A
= – 40°C To +85°C
Symbol
V
IH
V
IL
I
IH
I
IL
I
OZH
I
OZL
I
OFF
V
IK
V
H
I
CCL
I
CCH
I
CCZ
∆I
CC
Parameter
Input HIGH Voltage Level
Input LOW Voltage Level
Input Leakage Current
High Impedance Output Current
(3-State Output pins)
Input/Output Power Off Leakage
Clamp Diode Voltage
Input Hysteresis
Quiescent Power Supply Current
V
CC
= 0V, V
IN
or V
O
≤
5.5V
V
CC
= 2.3V, I
IN
= – 18mA
V
CC
= 3.3V
V
CC
= 3.6V
V
IN
= GND or V
CC
3.6
≤
V
IN
≤
5.5V
(2)
Quiescent Power Supply
Current Variation
One input at V
CC
- 0.6V,
other inputs at V
CC
or GND
—
—
—
—
—
—
—
– 0.7
100
—
—
—
±50
– 1.2
—
10
10
500
µA
8LVC Link
Test Conditions
V
CC
= 2.3V to 2.7V
V
CC
= 2.7V to 3.6V
V
CC
= 2.3V to 2.7V
V
CC
= 2.7V to 3.6V
V
CC
= 3.6V
V
CC
= 3.6V
V
I
= 0 to 5.5V
V
O
= 0 to 5.5V
Min.
1.7
2
—
—
—
—
Typ.
(1)
—
—
—
—
—
—
Max.
—
—
0.7
0.8
±5
±10
Unit
V
V
µA
µA
µA
V
mV
µA
NOTES:
1. Typical values are at V
CC
= 3.3V, +25°C ambient.
2. This applies in the disabled state only.
OUTPUT DRIVE CHARACTERISTICS
Symbol
V
OH
Parameter
Output HIGH Voltage
V
CC
Test Conditions
(1)
= 2.3V to 3.6V
I
OH
= – 0.1mA
I
OH
= – 6mA
I
OH
= – 12mA
Min.
V
CC
– 0.2
2
1.7
2.2
2.4
I
OH
= – 24mA
I
OL
= 0.1mA
I
OL
= 6mA
I
OL
= 12mA
V
CC
= 2.7V
V
CC
= 3.0V
I
OL
= 12mA
I
OL
= 24mA
2.2
—
—
—
—
—
Max.
—
—
—
—
—
—
0.2
0.4
0.7
0.4
0.55
8LVC Link
Unit
V
V
CC
= 2.3V
V
CC
= 2.3V
V
CC
= 2.7V
V
CC
= 3.0V
V
CC
= 3.0V
V
OL
Output LOW Voltage
V
CC
= 2.3V to 3.6V
V
CC
= 2.3V
V
NOTE:
1. V
IH
and V
IL
must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the
appropriate V
CC
range. T
A
= – 40°C to +85°C.
3
IDT74LVC2952A
3.3V CMOS OCTAL BUS TRANSCEIVER AND REGISTER
EXTENDED COMMERCIAL TEMPERATURE RANGE
OPERATING CHARACTERISTICS, VCC = 3.3V
±
0.3V, TA = 25°C
Symbol
C
PD
C
PD
Parameter
Power Dissipation Capacitance per Transceiver Outputs enabled
Power Dissipation Capacitance per Transceiver Outputs disabled
Test Conditions
C
L
= 0, f = 10Mhz
Typical
79
41
Unit
pF
pF
SWITCHING CHARACTERISTICS
Symbol
f
MAX
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
t
SU
t
H
t
SU
t
H
t
W
t
SK(0)
Parameter
Propagation Delay
CLKAB or CLKBA to Bx or Ax
Output Enable Time
OEBA
or
OEAB
to Ax or Bx
Output Disable Time
OEBA
or
OEAB
to Ax or Bx
Set-up Time,
Data Before CLK↑ HIGH
Hold Time,
Data After CLK↑ HIGH
Set-up Time,
CLKEN
Before CLK↑ HIGH
Hold Time,
CLKEN
After CLK↑ HIGH
Pulse Duration,
CLK HIGH or LOW
Output Skew
(2)
Min.
—
—
—
—
—
—
—
—
—
—
(1)
V
CC
= 2.7V
Min.
150
—
—
—
1.7
1.8
1.3
1.4
3.3
—
Max.
—
8.8
9
8.8
—
—
—
—
—
—
V
CC
= 3.3V ± 0.3V
Min.
150
1
1
1
1.3
1.1
1.1
1.1
3.3
—
Max.
—
8.2
7.8
7.8
—
—
—
—
—
1
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
V
CC
= 2.5V ± 0.2V
Max.
—
—
—
—
—
—
—
—
—
—
NOTES:
1. See test circuits and waveforms. T
A
= – 40°C to + 85°C.
2. Skew between any two outputs of the same package and switching in the same direction.
4
IDT74LVC2952A
3.3V CMOS OCTAL BUS TRANSCEIVER AND REGISTER
EXTENDED COMMERCIAL TEMPERATURE RANGE
TEST CONDITIONS
Symbol
V
LOAD
V
IH
V
T
V
LZ
V
HZ
C
L
V
CC
(1)
= 3.3V ±0.3V
6
2.7
1.5
300
300
50
V
CC
(1)
= 2.7V
6
2.7
1.5
300
300
50
TEST CIRCUITS AND WAVEFORMS
PROPAGATION DELAY
V
CC
(2)
= 2.5V ±0.2V Unit
2 x Vcc
V
Vcc
V
CC
/ 2
150
150
30
V
V
mV
mV
pF
8LVC Link
SAME PHASE
INPUT TRANSITION
t
PLH
OUTPUT
t
PLH
OPPOSITE PHASE
INPUT TRANSITION
t
PHL
t
PHL
V
IH
V
T
0V
V
OH
V
T
V
OL
V
IH
V
T
0V
LVC Link
TEST CIRCUITS FOR ALL OUTPUTS
V
CC
500
Ω
Pulse
(1, 2)
Generator
V
IN
D.U.T.
500
Ω
C
L
V
OUT
V
LOAD
Open
GND
ENABLE AND DISABLE TIMES
ENABLE
CONTROL
INPUT
t
PZL
OUTPUT
SW ITCH
NORMALLY
CLOSED
LOW
t
PZH
OUTPUT
SWITCH
NORMALLY
OPEN
HIGH
V
LOAD/2
V
T
t
PHZ
V
T
0V
t
PLZ
DISABLE
V
IH
V
T
0V
V
LOAD/2
V
OL+
V
LZ
V
OL
V
OH
V
OH-
V
HZ
0V
LVC Link
R
T
LVC Link
DEFINITIONS:
C
L
= Load capacitance: includes jig and probe capacitance.
R
T
=
Termination resistance: should be equal to Z
OUT
of the Pulse
Generator.
NOTES:
1. Pulse Generator for All Pulses: Rate
≤
10MHz; t
F
≤
2.5ns; t
R
≤
2.5ns.
2. Pulse Generator for All Pulses: Rate
≤
10MHz; t
F
≤
2ns; t
R
≤
2ns.
NOTE:
1. Diagram shown for input Control Enable-LOW and input Control
Disable-HIGH.
SWITCH POSITION
Test
Open Drain
Disable Low
Enable Low
Disable High
Enable High
All Other tests
Switch
V
LOAD
SET-UP, HOLD, AND RELEASE TIMES
DATA
INPUT
TIMING
INPUT
ASYNCHRONOUS
CONTROL
t
REM
t
SU
t
H
V
IH
V
T
0V
V
IH
V
T
0V
V
IH
V
T
0V
V
IH
V
T
0V
LVC Link
GND
Open
8LVC Link
OUTPUT SKEW - tsk (x)
INPUT
t
PLH1
t
PHL1
SYNCHRONOUS
CONTROL
t
SU
t
H
V
IH
V
T
0V
V
OH
PULSE WIDTH
LOW-HIGH-LOW
PULSE
t
W
HIGH-LOW-HIGH
PULSE
V
T
LVC Link
OUTPUT 1
t
SK
(x)
t
SK
(x)
V
T
V
OL
V
OH
V
T
OUTPUT 2
t
PLH2
t
PHL2
V
T
V
OL
t
SK
(x)
= t
PLH2
-
t
PLH1
or
t
PHL2
-
t
PHL1
LVC
NOTES:
1. For t
SK
(o) OUTPUT1 and OUTPUT2 are any two outputs.
2. For t
SK
(b) OUTPUT1 and OUTPUT2 are in the same bank.
Link
5
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