Bt8110/8110B
High-Capacity ADPCM Processor
This specification describes the Bt8110 and Bt8110B multichannel ADPCM processor
CMOS integrated circuits that implement Adaptive Differential Pulse-Code Modulation
(ADPCM) encoding and decoding. The fixed-rate coding algorithms include those
specified in ANSI Standard T1.303-1989. These algorithms are identical to those in
ITU-T Recommendations G.726 and G.727. These circuits also implement the
variable-rate or embedded codes specified in ANSI Standard T1.310-1991 and ITU-T
Recommendation G.727.
A single ADPCM processor integrated circuit can provide 24 or 32 full-duplex
channels of ADPCM processing (encoding and decoding). In some applications, two
circuits can be combined to provide 48 or 64 full-duplex channels. Both A-law and µ-law
PCM translations are provided.
Interface options such as serial and parallel inputs and outputs, along with hardware
and microprocessor control modes, are provided by the integrated circuits. Up to 14
separate ADPCM algorithms are available in any given configuration on a per-channel
basis.
The Bt8110 requires an external lookup table ROM. The Bt8110B has an internal
lookup table ROM, or can use an external lookup table ROM. When in direct framer
interface mode, transparent channels in the Bt8110 will operate at 56 kbit/s; the
Bt8110B operates at 64 kbit/s. A hardware control, direct framer interface mode has
been added to the Bt8110B. For more details on the Bt8110B mode controls, refer to
Table 1-1
and
Table 1-4.
Distinguishing Features
•
•
Bt8110B offers internal ROM
24 or 32 full-duplex channel capacity
(48 or 64 channels with two
processors)
2-, 3-, 4- and 5-bit quantization
dynamically selectable on a
channel-by-channel, frame-by-frame
basis
Transparent channel operation
Two control modes available:
microprocessor and hardware.
Direct framer interface for both T1
and E1 signal formats
Supports the optimal RESET function
described in the algorithm standards
Supports even-bit inversion of A-law
inputs and outputs (required by
ITU-T Recommendations G.726, and
G.727)
Minimum throughput delay
Pin compatible with Bt8110
8 mw per-channel, low-power CMOS
•
•
•
•
•
•
•
•
•
Functional Block Diagram
Applicable Standards
•
•
•
•
•
•
ANSI T1.302-1987
ANSI T1.303-1989
ANSI T1.310-1991
ITU-T G.726, G.727
ANSI T1.501-1994
ANSI T1Y1 Technical Reports #3 and
#10
64 Kbit/s
PCM
Input
Convert to
Uniform
PCM
ENCODER
Input
Signal
+
+
–
Difference
Signal
Adaptive
Quantizer
Signal
Estimate
Reconstructed
Signal
32 Kbit/s
ADPCM
Output
Adaptive
Predictor
+
Quantized
Difference Signal
Inverse
Adaptive
Quantizer
Applications
•
•
•
64 Kbit/s
PCM
Output
32 Kbit/s
ADPCM
Input
Inverse
Adaptive
Quantizer
DECODER
Quantized
Difference
Signal
+
+
Reconstructed
Signal
Convert to
PCM
–
Signal
Estimate
Synchronous
Coding
Adjustment
Adaptive
Predictor
•
•
•
•
•
•
T1/E1 Transcoders
T1/E1 Multiplexers
Personal Communications Systems:
Digital European Cordless
Telecommunications (DECT),
Personal Access Communications
System (PACS)
Wireless Local Loop
Voice PairGain
DCME Systems
Speech Processing/Recording
Voice Mail/Packetization
Voice over ATM/Frame Relay
Data Sheet
100060C
January 2000
Ordering Information
Model Number
Bt8110EPJ
Bt8110EPJB
Package
68-Pin Plastic Leaded Chip Carrier (PLCC)
68-Pin Plastic Leaded Chip Carrier (PLCC)
Ambient Temperature Range
–40 °C to +85 °C
–40 °C to +85 °C
Revision History
Revision
A
B
C
Level
Advanced
December 1996
January 2000
The timing diagrams for the following figures have been
updated:
Figure 2-3, Figure 2-5, Figure 2-6, Figure 2-7,
Figure 2-8, Figure A-2, Figure A-3, Figure A-4.
Date
Created
Description
© 1996, 2000 Conexant Systems, Inc.
All Rights Reserved.
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materials are provided by Conexant as a service to its customers and may be used for informational purposes only.
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specifications and product descriptions at any time, without notice. Conexant makes no commitment to update the
information contained herein. Conexant shall have no responsibility whatsoever for conflicts or incompatibilities arising
from future changes to its specifications and product descriptions.
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100060C
Conexant
Table of Contents
List of Figures
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v
List of Tables
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vii
1.0
Product Description
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
1.1
Channel Capacity and Configuration Modes
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2
1.1.1
1.1.2
1.1.3
1.2
Signal Inputs and Outputs
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2
Embedded Coding
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3
Control Mode
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3
Pin Descriptions
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4
2.0
Functional Description
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
2.1
Overview
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
2.1.1
2.1.2
2.1.3
2.2
2.2.1
Clocking and Synchronization
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
Microprocessor Interface
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
Address Map
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4
24- or 32-Channel Full-Duplex Interleaved Operation
. . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2.1.1
Signal Inputs and Outputs
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2.1.2
Reset Control
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
48- or 64-Channel Encoder-Only Operation
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
48- or 64-Channel Decoder-Only Operation
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Modes of Operation
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5
2.2.2
2.2.3
2.3
2.3.1
2.3.2
2.4
2.4.1
2.4.2
2-5
2-6
2-8
2-8
2-9
Direct Framer Interface Operation
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11
T1 Framer Interface
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11
E1 Framer Interface
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12
Mode Pins
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14
Control Pins
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14
Hardware Control
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13
3.0
Registers
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
3.1
3.2
0x00–0x3F—Per-Channel Control Registers (per_chan_ctrl)
. . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
0x40—Mode Control Register (mode)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3
100060C
Conexant
iii
Bt8110/8110B
High-Capacity ADPCM Processor
4.0
Electrical and Mechanical Specifications
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1
4.1
Microprocessor Interface Timing
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1
4.1.1
4.1.2
4.2
4.3
4.4
Bt8110 Timing
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2
ROM Specifications
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4
Absolute Maximum Ratings
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5
DC Characteristics
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6
Mechanical Specifications
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7
Appendix A. Hardware Mode Operation
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-1
A.1
48- or 64-Channel Full-Duplex Hardware Mode Operation
. . . . . . . . . . . . . . . . . . . . . . . . . . . . A-1
A.1.1
A.1.2
A.1.3
Introduction
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-1
Configuration
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-1
Functional Timing
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-3
Appendix B. T1 Speech Compression
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-1
B.1
Introduction
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-1
B.1.1
B.1.2
B.1.3
Configuration
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-1
Functional Timing Diagram
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-3
Microprocessor Interface And Per-Channel Configuration
. . . . . . . . . . . . . . . . . . . . . . . B-5
Appendix C. E1 Speech Compression
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-1
C.1
Introduction
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-1
C.1.1
C.1.2
C.1.3
Configuration
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-1
Functional Timing Diagram
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-3
Microprocessor Interface and Per-Channel Configuration.
. . . . . . . . . . . . . . . . . . . . . . . C-5
Appendix D. T1 ADPCM Transcoder
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-1
D.1
Introduction
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-1
D.1.1
D.1.2
D.1.3
Description
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-1
Summary
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-3
ADPCM Transcoder System Specifications
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-4
Appendix E. E1 ADPCM Transcoder
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-1
E.1
Introduction
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-1
E.1.1
E.1.2
E.1.3
Description
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-1
Summary
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-3
ADPCM Transcoder System Specifications
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-3
iv
Conexant
100060C
Bt8110/8110B
High-Capacity ADPCM Processor
List of Figures
List of Figures
Figure 1-1.
Figure 1-2.
Figure 1-3.
Figure 1-4.
Figure 2-1.
Figure 2-2.
Figure 2-3.
Figure 2-4.
Figure 2-5.
Figure 2-6.
Figure 2-7.
Figure 2-8.
Figure 4-1.
Figure 4-2.
Figure 4-3.
Figure A-1.
Figure A-2.
Figure A-3.
Figure A-4.
Figure B-1.
Figure B-2.
Figure C-1.
Figure C-2.
Figure D-1.
Figure D-2.
Figure E-1.
Figure E-2.
Bt8110 Pinout Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4
Bt8110 Logic Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6
Bt8110B Pinout Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7
Bt8110B Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9
Bt8110 Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
Bt8110B Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
Input and Output Timing for 24- or 32-Channel Full-Duplex
Interleaved Operation (Microprocessor Control) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6
Input and Output Timing for 48- or 64-Channel Half-Duplex
Encoder-Only Operation (Microprocessor Control) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9
Input and Output Timing for 48- or 64-Channel Half-Duplex
Decoder-Only Operation (Microprocessor Control) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10
Hardware Control Interleaved Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15
Hardware Control Encoder-Only Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16
Hardware Control Decoder-Only Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-17
Microprocessor Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2
Input and Output Signal Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3
68-Pin Plastic Leaded Chip Carrier (J-Bend) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7
48- or 64-Channel Configuration of the Bt8110/8110B . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-2
48- or 64-Channel Full-Duplex Interleaved Mode Functional Timing . . . . . . . . . . . . . . . . . . A-3
96- or 128-Channel Half-Duplex Encoder-Only Functional Timing. . . . . . . . . . . . . . . . . . . . A-4
96- or 128-Channel Half-Duplex Decoder-Only Functional Timing . . . . . . . . . . . . . . . . . . . A-5
T1 Speech Compression Interface Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-2
T1 Speech Compression Functional Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-4
E1 Speech Compression Interface Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-2
E1 Speech Compression Functional Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-4
Single-Board Transcoder Assembly. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-2
Single-Board Transcoder Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-3
Single-Board Transcoder Assembly. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-2
Single-Board Transcoder Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-3
100060C
Conexant
v
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