Threshold voltage, transformer Coupled, Measured on Stub (Note 7)
Common-Mode Voltage (Note 8)
RX DATA (or RX DATA) Rise time, Vin 1.2 Vpp
RX DATA (or RX DATA) Fall time, Vin 1.2 Vpp
RX DATA (or RX DATA) Rise time, Vin 9.0 Vpp
RX DATA (or RX DATA) Fall time, Vin 9.0 Vpp
RX DATA IN/RX DATA IN to RX DATA/RX DATA delay time
RX DATA (or RX DATA) STROBE delay (Active to Inhibit OR Inhibit to Active)
TRANSMITTER
Differential Output Voltage
Direct Coupled Across 35 Ohm, measured on bus
Transformer Coupled Across 70 Ohm, measured on Stub (Note 9)
Output Noise, differential (Direct coupled)
Output Offset Voltage, transformer Coupled Across 70 Ohm
Rise/Fall Time
TX DATA IN/TX DATA IN to TX DATA OUT/TX DATA OUT delay time
TX INHIBIT delay (Inhibit to Active)
TX INHIBIT delay (Active to Inhibit)
LOGIC
V
IH
V
IL
I
IH
(TX DATA IN, TX DATA IN, TX INHIBIT)
I
IH
(STROBE)
I
IL
(TX DATA IN, TX DATA IN, TX INHIBIT)
I
IL
(STROBE)
V
OH
(V
CC
= 4.75V, I
OH
=max)
V
OL
(V
CC
= 4.75V, I
OL
=min)
I
OL
I
OH
POWER SUPPLY REQUIREMENTS
Voltages/Tolerance
+5.0V
Current Drain (Note 10)
• Idle
• 25% Duty Transmitter Cycle
• 50% Duty Transmitter Cycle
• 100% Duty Transmitter Cycle
POWER DISSIPATION, V
CC
= 5.0V (NOTE 10)
• Idle
• 25% Duty Transmitter Cycle
• 50% Duty Transmitter Cycle
• 100% Duty Transmitter Cycle
THERMAL
Thermal Resistance, Junction-to-Heatsink
Thermal Resistance, Junction-to-Board (Note 11)
Heat sink soldered to PC board (2s2p - JESD51-5)
Operating Case Bottom Temperature
Operating Junction Temperature
Storage Temperature
Pad Temperature (soldering, 10 sec.)
PHYSICAL CHARACTERISTICS
Moisture Sensitivity Level
Package Body Size (Maximum)
32-pad LPCC
Weight
Refer to Table 1 notes on next page.
MIN
TYP
MAX
UNITS
-0.3
-5V_XCVR - 0.3
-1.5
2.5
0.200
5.0
7.0
5V_XCVR + 0.3
+1.5
Vdc
V
V
kOhm
pF
Vp-p
Vpeak
ns
ns
ns
ns
ns
ns
25
0.860
10
20
20
20
20
450
100
6
20
-250
100
7.2
21.5
150
9
27
10
250
300
250
250
400
Vcc
0.8
100
0
-20
0.4
Vp-p
Vp-p
mVp-p
mVp
ns
ns
ns
ns
V
V
µA
µA
µA
µA
V
V
mA
mA
2.0
0
20
0
-100
4.0
4.0
-2.4
4.75
5.0
40
166
280
480
0.20
0.48
0.70
1.00
7
14
5.25
50
200
330
550
0.25
0.65
0.95
1.35
9
17
+125
+150
+150
+300
Vdc
mA
mA
mA
mA
W
W
W
W
°C/W
°C/W
°C
°C
°C
°C
—
in.
(mm)
oz
(g)
-55
-55
-65
MSL-2
0.280 X 0.280 X 0.040 MAX
(7.1 x 7.1 x 1.0)
0.0049
(0.14)
Data Device Corporation
www.ddc-web.com
3
BU-63155L3
Rev H-07/12-0
TABLE 1 Notes
Notes 1 through 6 and 12 are applicable to the Receiver Differential Resistance and Differential Capacitance specifications:
(1) Specifications include both transmitter and receiver (assumed tied together externally without a transformer).
(2) Impedance parameters are specified directly between pads Tx Data Out / RX Data In and Tx Data Out / RX Data In of the package.
(3) It is assumed that all power and ground inputs to the package are connected.
(4) The specifications are applicable for both un-powered and powered conditions.
(5) The specifications assume a 1.5-volt rms balanced differential, sinusoidal input. The applicable frequency range is 75 kHz to 1 MHz.
(6) Minimum resistance and maximum capacitance parameters are guaranteed over the operating range, but are not tested.
(7) The Threshold Level, as referred to in this specification, is meant to be the maximum peak-to-peak voltage (measured on the stub) that can be applied to the receiver's
input without causing the output to change from the OFF state.
(8) Assumes a common-mode voltage within the frequency range of dc to 2 MHz, applied to pins of the isolation transformer on the stub side (either direct or transformer
coupled), and referenced to hybrid ground. Transformer must be a DDC recommended transformer.
(9) MIL-STD-1760 requires minimum output voltage of 20Vp-p on the stub connection.
(10) Current drain and power dissipation specifications are preliminary and subject to change. Power dissipation specifications assume a transformer coupled configuration
with external dissipation (while transmitting with 100% duty cycle) of 1.4W (for 1760 amplitudes), which is the power delivered to the 1553 fault isolation resistors, the
power delivered to the bus termination resistors, the copper losses in the transceiver isolation transformer and the bus coupling transformer.
(11) Thermal resistance specs are preliminary and subject to change. Junction-to-board thermal resistance is measured in accordance with JEDEC standard JESD51-8.
The 16 thermal vias connecting the LPCC heatsink to PCB internal plane are in accordance with JEDEC JESD51-5 (2s2p). Each via is 0.3 mm diameter with 0.035
mm plating. Please refer to JEDEC standard JESD51-5 for detailed PCB construction.
(12) To calculate the loading effect on the stub side of the "long stub" isolation transformer, multiply "R" by 3.20 (Isolation Transformer ratio of 1.79²) and divide "C" by 3.20.
For "short stub" isolation transformers, multiply "R" by 6.25 (Isolation Transformer ratio of 2.50²) and divide "C" by 6.25.
(13) Assuming the use of isolation transformers with the turns ratios shown in Figure 3 and in the absence of common mode signal on the 1553 stub, this equates to a
nominal stub voltage of 38 Volts
PK-to-PK
transformer-coupled, or 53 Volts
PK-to-PK
direct-coupled.
INTRODUCTION
The BU-63155L3 is a single transmitter and receiver packaged in
a 32-pad LPCC. It is directly compatible to the Harris 15530
encoder/decoder and has internal (factory preset) threshold lev-
els. The transceiver only requires +5V power and conforms to
MIL-STD-1553A and 1553B.
FIGURE 3 illustrates the connection between a BU-63155L3
transceiver and a MIL-STD-1553 Data Bus. After transformer
isolating the transceiver, it can be either direct coupled (short
stub) or transformer coupled (long stub) to the Data Bus.
WAVEFORMS
FIGURE 2 illustrates the BU-63155L3 with Harris type decoder
interface. Note that TX DATA IN and TX DATA IN inputs must be
complementary waveforms with a 50% duty cycle.
1553 BUS INTERFACE AND LAYOUT
CONSIDERATIONS
FIGURE 3 illustrates the interface between the BU-63155L3 and
a MIL-STD-1553 bus. Connections for direct (short stub) and
transformer (long stub) coupling, as well as typical peak-to-peak
voltage levels at various points (when transmitting), are indicated
in the diagram.
Note that the BU-63155L3 has multiple pads for each of the TX DATA
OUT phases. All pads of the same signal phase must be connected
together on the PCB to assure adequate current carrying capacity.
The center tap of the primary winding (the side of the transformer
that connects to the BU-63155L3) must be directly connected to
the ground plane.
ENCODER
OUTPUT
(NOTE 2)
TX Data In
TX Data In
LINE-TO-LINE
OUTPUT
LINE-TO-LINE
INPUT
TRANSMIT OPERATING MODE
The transmitter section accepts encoded TTL data and converts
it to bi-phase Manchester II form using a waveshaping network
and driver circuits. The driver outputs TX DATA OUT and TX DATA
OUT are transformer coupled to the Data Bus.
The transmitter output terminals can be put into a high imped-
ance state by setting TX INHIBIT high, or setting TX DATA IN and
TX DATA IN to the same logic level.
XXX
XXX
X X X
X X X
RECEIVER OPERATING MODE
The receiver section accepts data from a MIL-STD-1553 Data
Bus when coupled to the Data Bus as shown in FIGURE 3. This
data is converted to TTL and furnished to RX DATA OUT and RX
DATA OUT.
When STROBE is high data passes through the receiver to RX
DATA OUT and RX DATA OUT. Applying a low to STROBE dis-
ables the receiver output terminals.
As illustrated in FIGURE 2, the receiver in the BU-63155L3 pro-
vides compatibility to the Harris type decoder.
Data Device Corporation
www.ddc-web.com
4
BU-63155L3
RX Data Out
RX Data Out
Notes:
(1) TX Data In and RX Data Out are TTL signals.
(2) TX Data In inputs must be at the same logic level when not transmitting.
(3) LINE-TO-LINE output voltage is measured between TX Data Out and TX Data Out.
(4) LINE-TO-LINE input voltage is measured on the Data Bus.
FIGURE 2. WAVEFORMS FOR HARRIS TYPE
ENCODER/DECODER
BU-63155L3
Rev H-07/12-0
Furthermore, when transmitting, large currents will flow from the
5V plane, into the LPCC package Vcc pads, out through the TX
DATA OUT / TX DATA OUT pads, through the transformer prima-
ries and then out through the center tap and into the ground
plane. The traces in this path should be sized accordingly and
the connections to the 5V and ground planes should be as short
as possible. Note that the heatsink on the bottom of the package
is also electrically grounded.
It is recommend that the BU-63155L3 be bypassed with a 10 µF
low inductance tantalum capacitor in parallel with a 0.01µF
ceramic capacitor. These capacitors should be located as close
to the Vcc and GND pads as possible.
To achieve its full military temperature range rating, the BU-63155L3
needs to be properly heat sinked. The thermal resistance junction-
to-board specification (TABLE 1) allows for 16 thermal vias con-
necting the heatsink on the package bottom to a 2s2p (2 sided, 2
plane PCB), 3.0" x 4.5". The thermal via construction follows
JEDEC standard JESD51-5 with thermal vias connecting the top
side mini-plane located under the heatsink to the upper internal
plane. The board temperature is determined 1 mm from the pack-
age in accordance with JEDEC standard JESD51-8.
The 2s2p PCB construction has 2 inner planes of 1 oz copper, 2
outer trace layers of 2 oz copper and has an overall thickness of
1.6 mm, which is divided evenly amongst the 3 dielectrics. The
top layer has 8 traces (0.26 mm width each) fanning out from
each side of the package. Refer to the appropriate JEDEC stan-
dards, and DDC’s Application Note AN/B-39 "MIL-STD-1553
LPCC PACKAGED TRANSCEIVERS, A USER'S GUIDE" for
further information.
ISOLATION TRANSFORMERS
In selecting isolation transformers to be used with the
BU-63155L3, there is a limitation on the maximum amount of
leakage inductance. If this limit is exceeded, the transmitter rise
and fall times may increase, possibly causing the bus amplitude
to fall below the minimum level required by MIL-STD-1553. In
addition, an excessive leakage imbalance may result in a trans-
former dynamic offset that exceeds 1553 specifications.
The maximum allowable leakage inductance is 6.0 µH, and is
measured as follows:
The side of the transformer that connects to the BU-63155L3 is
defined as the "primary" winding. If one side of the primary is
shorted to the primary center-tap, the inductance should be
measured across the "secondary" (transformer coupled) wind-
ing. This inductance must be less than 6.0 µH. Similarly, if the
other side of the primary is shorted to the primary center-tap, the
inductance measured across the "secondary" (transformer cou-
pled) winding must also be less than 6.0 µH.
The difference between these two measurements is the "differ-
ential" leakage inductance. This value must be less than 1.0 µH.
Beta Transformer Technology Corporation (BTTC), a subsidiary
of DDC, manufactures transformers in a variety of mechanical
configurations with the required turns ratios of 1:2.5 direct cou-
pled, and 1:1.79 transformer coupled. TABLE 2 provides a listing
of these transformers.
For further information, contact BTTC at 631-244-7393 or at
www.bttc-beta.com.
DATA
BUS
Z
0
(1:2.5)
TX
TX/RX
12 Vpp
BU-63155L3
TX
RX
RX
TX/RX
ISOLATION
TRANSFORMER
SHORT STUB
(DIRECT COUPLED)
55
Ω
30 Vpp
55
Ω
1 FT MAX
7.2Vpp
OR
(1:1.79)
TX
12 Vpp
BU-63155L3
TX
LONG STUB
(TRANSFORMER
COUPLED)
20 FT MAX
21.5 Vpp
(1:1.41)
0.75 Z
0
30 Vpp
0.75 Z
0
7.5Vpp
RX
RX
ISOLATION
TRANSFORMER
COUPLING
TRANSFORMER
Z
0
Z
0
= 70 TO 85 OHMS
FIGURE 3. BU-63155L3 INTERFACE TO A MIL-STD-1553 BUS
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