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SM0-67204E-40SB/SC

Description
FIFO, 4KX9, 40ns, Asynchronous, CMOS, DIE
Categorystorage    storage   
File Size104KB,15 Pages
ManufacturerAtmel (Microchip)
Download Datasheet Parametric View All

SM0-67204E-40SB/SC Overview

FIFO, 4KX9, 40ns, Asynchronous, CMOS, DIE

SM0-67204E-40SB/SC Parametric

Parameter NameAttribute value
MakerAtmel (Microchip)
Parts packaging codeDIE
package instructionDIE,
Reach Compliance Codeunknown
ECCN codeEAR99
Maximum access time40 ns
period time50 ns
JESD-30 codeX-XUUC-N
memory density36864 bit
memory width9
Number of functions1
word count4096 words
character code4000
Operating modeASYNCHRONOUS
Maximum operating temperature125 °C
Minimum operating temperature-55 °C
organize4KX9
ExportableNO
Package body materialUNSPECIFIED
encapsulated codeDIE
Package shapeUNSPECIFIED
Package formUNCASED CHIP
Parallel/SerialPARALLEL
Certification statusNot Qualified
Maximum supply voltage (Vsup)5.5 V
Minimum supply voltage (Vsup)4.5 V
Nominal supply voltage (Vsup)5 V
surface mountYES
technologyCMOS
Temperature levelMILITARY
Terminal formNO LEAD
Terminal locationUPPER
M67204E
4 K

9 CMOS Parallel FIFO Rad Tolerant
Introduction
The M67204E implement a first-in first-out algorithm,
featuring asynchronous read/write operations. The FULL
and EMPTY flags prevent data overflow and underflow.
The Expansion logic allows unlimited expansion in word
size and depth with no timing penalties. Twin address
pointers automatically generate internal read and write
addresses, and no external address information are
required for the TEMIC FIFOs. Address pointers are
automatically incremented with the write pin and read
pin. The 9 bits wide data are used in data communications
applications where a parity bit for error checking is
necessary. The Retransmit pin resets the Read pointer to
zero without affecting the write pointer. This is very
useful for retransmitting data when an error is detected in
the system.
Using an array of eigh transistors (8 T) memory cell, the
M67204E combine an extremely low standby supply
current (typ = 1.0
µA)
with a fast access time at 40 ns
over the full temperature range. All versions offer battery
backup data retention capability with a typical power
consumption at less than 2
µW.
The M67204E is processed according to the methods of
the latest revision of the MIL STD 883 (class B or S), ESA
SCC 9000 and QML.
Features
D
D
D
D
First-in first-out dual port memory
4096
×
9 organisation
Fast access time: 40, 50 ns
Wide temperature range : – 55
°C
to + 125
°C
D
D
D
D
D
D
D
D
D
Fully expandable by word width or depth
Asynchronous read/write operations
Empty, full and half flags in single device mode
Retransmit capability
Bi-directional applications
Battery back-up operation 2 V data retention
TTL compatible
Single 5 V
±
10 % power supply
High performance SCMOS technology
Rev. F – June 30, 1999
1
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