UNISONIC TECHNOLOGIES CO., LTD
UR5515
1.5A/3A BUS TERMINATION
REGULATOR
SOP-8
DESCRIPTION
CMOS IC
The UTC
UR5515
is a linear bus termination regulator and
designed to convert voltage supplies ranging from 1.6V~6.0V into a
desired output voltage, which adjusted by two external voltage
divider resistors. The device can both source and sink up to 1.5A/3A
of current while regulating an output voltage to within 2% (DDR-I)
and 3% (DDR-II) or less.
The UTC
UR5515
is capable of use in conjunction with series
termination resistors to provide an excellent voltage source for active
termination schemes of high speed transmission lines as those seen
in high speed memory buses and distributed backplane designs.
The voltage output of the regulator can be used as a termination
voltage for DDR SDRAM.
1
TO-252-5
1
TO-263-5
*Pb-free plating product number: UR5515L
FEATURES
* Support Both DDR-I (1.25 V
TT
) and DDR-II (0.9 V
TT
) Requirements
* Capable of Sourcing and Sinking Current 1.5A/3A
* Current-limiting Protection and Thermal Shutdown Protection
* Integrated Power MOSFETs
* Generates Termination Voltages for SSTL-2
* High Accuracy Output Voltage at Full-Load
* Adjustable output voltage by External Resistors
* Minimum External Components
* Shutdown for Standby or Suspend Mode Operation with
High-impedance Output.
ORDERING INFORMATION
Order Number
Normal
Lead Free Plating
UR5515-S08-R
UR5515L-S08-R
UR5515-S08-T
UR5515L-S08-T
UR5515-TN5-R
UR5515L-TN5-R
UR5515-TN5-T
UR5515L-TN5-T
UR5515-TQ5-R
UR5515L-TQ5-R
UR5515-TQ5-T
UR5515L-TQ5-T
Package
SOP-8
SOP-8
TO-252-5
TO-252-5
TO-263-5
TO-263-5
Packing
Tape Reel
Tube
Tape Reel
Tube
Tape Reel
Tube
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QW-R502-056,A
UR5515
PIN DESCRIPTION
PIN NO.
SOP-8
1
2
5,6,7,8
3
4
TO-252-5/TO-263-5
1
2
3
4
5
PIN NAME
V
IN
GND
V
CNTL
V
REF
V
OUT
DESCRIPTION
CMOS IC
Input Voltage
Ground
Gate Drive Voltage
Reference Voltage Input and Chip Enable
Output Voltage
BLOCK DIAGRAM
V
CNTL
V
IN
V
REF
Current
Limiting
Sensor
Thermal
CNTL
V
OUT
GND
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UR5515
ABSOLUTE MAXIMUM RATINGS
PARAMETER
CMOS IC
SYMBOL
RATINGS
UNIT
Input Voltage
V
IN
7
V
Power Dissipation
P
D
Internally Limited
W
℃
Junction Temperature
T
J
125
℃
Storage Temperature Range
T
STG
-40 ~ 150
Note:1.Absolute maximum ratings are those values beyond which the device could be permanently damaged.
Absolute maximum ratings are stress ratings only and functional device operation is not implied.
2.The device is guaranteed to meet performance specification within 0℃~70℃ operating temperature range
and assured by design from –20℃~85℃.
ELECTRICAL CHARACTERISTICS
UNIT
(Ta = 25℃, unless otherwise specified: V
IN
= 2.5V, V
CNTL
= 3.3V, V
REF
= 1.25V, C
OUT
=10μF(Ceramic).)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN TYP MAX
DDR-I
1.6
2.5
V
IN
DDR-II
1.8
Input Voltage Range(Note 1)
No Load,(Note 2)
DDR-I
3.3
6
V
CNTL
DDR-II
3.3
6
Output Offset Voltage
V
OS
I
OUT
=0A, Fig. 1 (Note 3)
-20
0
20
Operating Current of V
CNTL
I
CNTL
No Load
6.5
10
DDR-I
0.8
2
I
L
: 0~1.5A, Fig. 1
DDR-II
1.2
3
|△V
LOAD
|
Load Regulation
DDR-I
0.8
2
I
L
: 0~-1.5A, Fig. 1
DDR-II
1.2
3
Current In Shutdown Mode
I
SHDN
V
REF
<0.2V, R
L
=180Ω, Fig. 2
50
90
Short Circuit Protection
UR5515
Fig 3, 4
2.1
Current Limit
I
LIMIT
UR5515A
Fig 3, 4
3.0
Over Temperature Protection
Thermal Shutdown Temperature
T
SD
3.3V≤V
CNTL
≤5V
125
150
Thermal Shutdown Hysteresis
50
Shutdown Function
Shutdown Threshold Voltage
V
THD
Fig 5
0.2
0.8
Note 1. For safely operate your system, the 3.3V rail have to be tied to V
CNTL
rather than 5V rail
2. Keep V
CNTL
≥V
IN
on operation power on and power off sequences.
3. V
OS
offset is the voltage measurement defined as V
OUT
subtracted from V
REF
.
V
mV
mA
%
μA
A
℃
℃
V
THERMAL DATA
PARAMETER
SYMBOL
SOP-8
TO-252-5
TO-263-5
θ
JC
RATINGS
35
8
4
UNIT
℃/W
Thermal Resistance Junction-Case
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UR5515
TEST CIRCUITS
2.5V
3.3V
CMOS IC
2.5 V
V
IN
1.25V
3.3V
V
CNTL
V
V
IN
V
REF
UTC
V
OUT
UR5515
GND
V
OUT
V
1.25V
0.2V
V
CNTL
UTC
UR5515
V
OUT
V
REF
GND
V
OUT
R
L
1.25V
V
0V
R
L
and C
OUT
Time delay
I
L
C
OUT
C
OUT
Fig1. Output Voltage Tolerance ,
△
V
OUT
Fig 2. Current in Shutdown Mode, I
SHCLN
2.5V
V
IN
1.25V
V
REF
3.3V
V
CNTL
UTC
UR5515 V
OUT
GND
A
V
OUT
V
I
L
C
OUT
Power supply
with current limit
2.5V
V
IN
1.25V
V
REF
A
3.3V
I
L
V
CNTL
UTC
V
OUT
UR5515
V
OUT
V
GND
C
OUT
Fig 3. Current Limit for HIgh Side, I
CLHIGH
Fig 4. Current Limit for Low Side, I
CLLOW
2.5V
V
IN
1.25V
V
REF
0.2V
1.25V
V
OUT
0V
V
REF
3.3V
V
CNTL
UTC
UR5515 V
OUT
GND
R
L
V
OUT
V
C
OUT
R
L
and C
OUT
Time delay
V
OUT
would be low if V
REF
< 0.2V
V
OUT
would be high if V
REF
> 0.8V
Fig 5. V
REF
Pin Shutdown Threshold Voltage
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TYPICAL APPLICATION CIRCUIT
CMOS IC
R
1
= R
2
= 100KΩ
C
OUT(min)
=10μF(Ceramic) + 1000μF under the worst case testing condition
C
SS
=1μF, C
IN
= 40μF(low ESR), C
CNTL
= 47μF
APPLICATIONS INFORMATION
Please note the point of thermal shutdown will be degraded by around 20℃while V
CNTL
equal to 5V compared
with 3.3V. It is highly recommended that to use the 3.3V rail acted as the V
CNTL
in SOP-8 package. Nevertheless,
this small footprint of PCB for plastic SOP-8 package is not enough to dissipate effectively the heat generated
when operating at high current levels. In order to control die operating temperatures, the PCB layout should allow
for maximum possible copper area at the four V
CNTL
pins. Besides, an appropriate power plane heat sink must be
used to prevent overstepping maximum junction temperature. The recommended SMT is as below.
Use vias to conduct the heat into the
buried or backside of PCB layer.
The PCB heat sink copper area should be
solder painted without masked . This
approaches a "best case " pad heat sink .
UTC UR5515
(SOP-8)
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