128K x 32 SRAM MODULE
PUMA 68S4000/A - 020/025/35/45
Elm Road, West Chirton, NORTH SHIELDS, Tyne & Wear
NE29 8SE, England Tel.+44 (0191) 2930500 Fax.+44 (0191) 2590997
Issue 4.5 : April 2001
Description
The PUMA68S4000/A is a 4Mbit CMOS High
Speed Static RAM organised as 128K x 32 in a
JEDEC 68 pin surface mount PLCC, available with
access times of 20, 25, 35, and 45ns. The output
width is user configurable as 8 , 16 or 32 bits using
four Chip Selects (CS1~4).
The device features multiple ground pins for
maximum noise immunity and TTL compatible
inputs and outputs. The PUMA 68S4000/A offers a
dramatic space saving advantage over four
standard 128Kx8 devices.
Features
• Fast Access Times of 20 ,25, 35 and 45 ns.
• JEDEC 68 'J' leaded plastic surface mount Substrate
• Industrial or Military Grade.
• Upgradeable footprint.
• User Configurable as 8 / 16 / 32 bit wide output.
• Operating Power
Low Power Standby
• Fully Static operation.
• Multiple ground pins for maximum noise immunity.
• Single 5V±10% Power supply.
(32-BIT)
(TTL)
4.00 W (Max)
1.43 W (Max)
Block Diagram
(PUMA 68 S4000A page 2)
A0-A16
OE
WE
Pin Definition
(PUMA 68 S4000A page 2)
CS3
GND
CS4
NC
A0
WE
A6
A7
A8
A2
A1
A3
A4
A5
VCC
A10
A9
9
8
7
6
5
4
3
2
1 68 67 66 65 64 63 62 61
60
59
58
57
56
D0
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
D16
D17
D18
D19
D20
D21
D22
D23
GND
D24
D25
D26
D27
D28
D29
D30
D31
128Kx8
SRAM
CS1
CS2
CS3
CS4
D0-7
D8-15
D16-23
D24-31
128Kx8
SRAM
128Kx8
SRAM
128Kx8
SRAM
D1
D2
D3
D4
D5
D6
D7
GND
D8
D9
D10
D11
D12
D13
D14
D15
PUMA 68S4000
VIEW
FROM
ABOVE
55
54
53
52
51
50
49
48
47
46
45
44
CS1
CS2
A11
NC
GND
VCC
NC
NC
NC
OE
NC
A12
A13
Pin Functions
Address Inputs
Data Input/Output
Chip Select
Write Enable
Output Enable
No Connect
Power (+5V)
Ground
A0 - A16
D0 - D31
CS1~4
WE1~4
OE
NC
V
CC
GND
Package Details
Plastic 68 J-Leaded JEDEC PLCC
A14
A15
A16
NC
PUMA 68S4000/A - 020/025/35/45
ISSUE 4.5 : April 2001
PUMA 68 S4000A Pinout and Block Diagram.
A0 ~A16
/OE
/WE4
/WE3
/WE2
/WE1
128K x 8
SRAM
128K x 8
SRAM
128K x 8
SRAM
128K x 8
SRAM
/CS1
/CS2
/CS3
/CS4
D0~7
D8~15
D16~23
D24~31
9
NC
A0
A1
A2
A3
A4
A5
/CS3
GND
/CS4
/WE1
A6
A7
A8
A9
A10
VCC
8
7
6
5
4
3
2
1 68 67 66 65 64 63 62 61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
D0
D1
D2
D3
D4
D5
D6
D7
GND
D8
D9
D10
D11
D12
D13
D14
D15
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
PUMA 68S4000A
VIEW
FROM
ABOVE
D16
D17
D18
D19
D20
D21
D22
D23
GND
D24
D25
D26
D27
D28
D29
D30
D31
VCC
A11
A12
A13
A14
A15
A16
/CS1
/OE
/CS2
NC
/WE2
/WE3
/WE4
NC
GND
NC
2
PUMA 68S4000/A - 020/025/35/45
ISSUE 4.5 : April 2001
DC OPERATING CONDITIONS
Absolute Maximum Ratings
(1)
Parameter
Voltage on any pin relative to V
SS
Power Dissipation
Storage Temperature
Symbol
V
T(2)
P
T
T
STG
Min
-0.3
-
-65
Typ
-
-
-
Max
7.0
4.0
150
Unit
V
W
o
C
Notes : (1) Stresses above those listed may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at those or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
Recommended Operating Conditions
Parameter
Supply Voltage
Input High Voltage
Input Low Voltage
Operating Temperature
Symbol
V
CC
V
IH
V
IL
T
A
T
AI
T
AM
Min
4.5
2.2
-0.3
0
-40
-55
Typ
5.0
-
-
-
-
-
Max
5.5
V
CC
+0.3
0.8
70
85
125
Unit
V
V
V
o
C
o
C (Suffix I)
o
C (Suffix M)
(Commercial)
(Industrial)
(Military)
DC Electrical Characteristics
(V
CC
=5V±10%, T
A
= -55
o
C to +125
o
C)
Parameter
Input Leakage Current
Output Leakage Current
Symbol Test Condition
I
LI1
I
LO
V
IN
=0V to V
CC
V
I/O
=0V to V
CC
CS
(1)
=V
IL
, I
I/O
=0mA, f=f
max
As above.
As above.
CS
(1)
=V
IH
, f=f
max
, V
IN
=V
IL
or V
IH
Min Typ
-20
-40
-
-
-
-
-
2.4
-
-
-
-
-
-
-
-
max
20
40
840
540
400
260
0.4
-
Unit
µA
µA
mA
mA
mA
mA
V
V
Operating Supply Current
(2)
32 bit I
CC32
16 bit I
CC16
8 bit I
CC8
Standby Supply Current
Output Voltage Low
Output Voltage High
(TTL) I
SB
V
OL
V
OH
I
OL
= 8.0mA,V
CC
=Min
I
OH
= -4.0mA,V
CC
=Min
Notes: (1) CS1~4 inputs operate simultaneously for 32 bit mode, in pairs for 16 bit mode and singly for 8 bit
mode.
(2) At f=f
max
address and data inputs are cycling at max frequency.
3
PUMA 68S4000/A - 020/025/35/45
ISSUE 4.5 : April 2001
Capacitance
(V
CC
=5V±10%,T
A
=25
o
C)
Parameter
Input Capacitance
Address,OE,WE
Output Capacitance
8-bit mode (worst case)
Symbol
C
IN1
C
I/O
Note: Capacitance calculated, not measured.
Test Condition
V
IN
=0V
V
I/O
=0V
min
-
-
typ
-
-
max
34
42
Unit
pF
pF
AC Test Conditions
Output Load
* Input pulse levels: 0V to 3.0V
* Input rise and fall times: 3ns
* Input and Output timing reference levels: 1.5V
* Output load: see diagram
* V
CC
=5V±10%
Operation Truth Table
I/O Pin
166Ω
1.76V
30pF
CS1 CS2 CS3 CS4
L
H
H
H
L
H
L
L
H
H
H
L
H
L
X
H
H
L
H
H
L
H
L
H
L
H
H
L
H
L
X
H
H
H
L
H
H
L
L
H
H
L
H
H
L
L
X
H
H
H
H
L
H
L
L
H
H
H
L
H
L
L
X
H
OE
X
X
X
X
X
X
X
L
L
L
L
L
L
L
H
X
WE
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
X
SUPPLY CURRENT
I
CC8
I
CC8
I
CC8
I
CC8
I
CC16
I
CC16
I
CC32
I
CC8
I
CC8
I
CC8
I
CC8
I
CC16
I
CC16
I
CC32
I
CC32
/I
CC16
/I
CC8
I
SB
,I
SB1
MODE
Write D
0~7
Write D
8~15
Write D
16~23
Write D
24~31
Write D
0~15
Write D
16~31
Write D
0~31
Read D
0~7
Read D
8~15
Read D
16~23
Read D
24~31
Read D
0~15
Read D
16~31
Read D
0~31
D
0~31
High-Z
D
0~31
Standby
Notes : H = V
IH
: L =V
IL
: X = V
IH
or V
IL
4
PUMA 68S4000/A - 020/025/35/45
ISSUE 4.5 : April 2001
AC OPERATING CONDITIONS
Read Cycle
-020
Parameter
Read Cycle Time
Address Access Time
Chip Select Access Time
Output Enable to Output Valid
Output Hold from Address Change
Chip Selection to Output in Low Z
Output Enable to Output in Low Z
Chip Deselection to O/P in High Z
Output Disable to Output in High Z
-025
min
25
-
-
-
3
3
0
0
0
-35
min
35
-
-
-
3
3
0
0
0
-45
max
-
35
35
15
-
-
-
12
12
Symbol
t
RC
t
AA
t
ACS
t
OE
t
OH
t
CLZ
t
OLZ
t
CHZ
t
OHZ
min
20
-
-
-
3
3
0
0
0
max
-
20
20
10
-
-
-
9
8
max
-
25
25
12
-
-
-
10
10
min
45
-
-
-
3
3
0
0
0
max
-
45
45
17
-
-
-
15
15
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
Write Cycle
-020
Parameter
Write Cycle Time
Chip Selection to End of Write
Address Valid to End of Write
Address Setup Time
Write Pulse Width
Write Recovery Time
Write to Output in High Z
Data to Write Time Overlap
Data Hold from Write Time
Output active from end of write
-025
min
25
20
20
0
15
0
0
12
0
3
-35
min
35
25
25
0
17
0
0
15
0
3
-45
min
45
35
35
0
20
0
0
15
0
3
Symbol
t
WC
t
CW
t
AW
t
AS
t
WP
t
WR
t
WHZ
t
DW
t
DH
t
OW
min
20
15
15
0
12
0
0
10
0
3
max
-
-
-
-
-
-
10
-
-
-
max
-
-
-
-
-
-
12
-
-
-
max
-
-
-
-
-
-
15
-
-
-
max
-
-
-
-
-
-
15
-
-
-
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
5
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