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FN8232
Rev 9.00
September 23, 2015
ISL12027, ISL12027A
Real Time Clock/Calendar with EEPROM
The ISL12027 device is a low power real time clock with
timing and crystal compensation, clock/calender, power-fail
indicator, two periodic or polled alarms, intelligent battery
backup switching, CPU Supervisor and integrated 512x8-bit
EEPROM, in 16 Byte per page format.
The oscillator uses an external, low-cost 32.768kHz crystal.
The real time clock tracks time with separate registers for
hours, minutes, and seconds. The device has calendar
registers for date, month, year and day of the week. The
calendar is accurate through 2099, with automatic leap year
correction.
The ISL12027 and ISL12027A Power Control Settings are
different. The ISL12027 uses the Legacy Mode Setting, and
the ISL12027A uses the Standard Mode Setting.
Applications that have V
BAT
> V
DD
will require only the
ISL12027A. Please refer to“Power Control Operation” on
page 15 for more details. Also, please refer to “I
2
C
Communications During Battery Backup and LVR Operation”
on page 24 for important details.
Features
• Real Time Clock/Calendar
- Tracks Time in Hours, Minutes and Seconds
- Day of the Week, Day, Month and Year
• Two Non-Volatile Alarms
- Settable on the Second, Minute, Hour, Day of the Week,
Day, or Month
- Repeat Mode (Periodic Interrupts)
• Automatic Backup to Battery or SuperCap
• On-Chip Oscillator Compensation
- Internal Feedback Resistor and Compensation
Capacitors
- 64 Position Digitally Controlled Trim Capacitor
- 6 Digital Frequency Adjustment Settings to ±30ppm
• 512x8-Bits of EEPROM
- 16-Byte Page Write Mode (32 total pages)
- 8 Modes of BlockLock™ Protection
- Single Byte Write Capability
• High Reliability
- Data Retention: 50 years
- Endurance: >2,000,000 Cycles Per Byte
• I
2
C-bus™ Interface
- 400kHz Data Transfer Rate
• 800nA Battery Supply Current
• Package Options
- 8 Ld SOIC and 8 Ld TSSOP Packages
• Pb-Free (RoHS Compliant)
Pinouts
ISL12027, ISL12027A
(8 LD TSSOP)
TOP VIEW
V
BAT
V
DD
X1
X2
1
2
3
4
8
7
6
5
SCL
SDA
GND
RESET
ISL12027, ISL12027A
(8 LD SOIC)
TOP VIEW
X1
X2
RESET
GND
1
2
3
4
8
7
6
5
V
DD
V
BAT
SCL
SDA
Applications
• Utility Meters
• HVAC Equipment
• Audio/Video Components
• Modems
• Network Routers, Hubs, Switches, Bridges
• Cellular Infrastructure Equipment
• Fixed Broadband Wireless Equipment
• Pagers/PDA
• POS Equipment
• Test Meters/Fixtures
• Office Automation (Copiers, Fax)
• Home Appliances
• Computer Products
• Other Industrial/Medical/Automotive
FN8232 Rev 9.00
September 23, 2015
Page 1 of 29
ISL12027, ISL12027A
Pin Descriptions
PIN NUMBER
SOIC
1
2
3
TSSOP
3
4
5
SYMBOL
X1
X2
RESET
BRIEF DESCRIPTION
The X1 pin is the input of an inverting amplifier and is intended to be connected to one pin of an external
32.768kHz quartz crystal. X1 can also be driven directly from a 32.768kHz source.
The X2 pin is the output of an inverting amplifier and is intended to be connected to one pin of an external
32.768kHz quartz crystal.
RESET. This is a reset signal output. This signal notifies a host processor that the “watchdog” time period
has expired or that the voltage has dropped below a fixed V
TRIP
threshold. It is an open drain active LOW
output. Recommended value for the pull-up resistor is 5k. If unused, connect to ground.
Ground.
Serial Data (SDA) is a bidirectional pin used to transfer serial data into and out of the device. It has an
open drain output and may be wire OR’ed with other open drain or open collector outputs.
The Serial Clock (SCL) input is used to clock all serial data into and out of the device. The input buffer on
this pin is always active (not gated).
This input provides a backup supply voltage to the device. V
BAT
supplies power to the device in the event
that the V
DD
supply fails. This pin should be tied to ground if not used.
Power Supply.
4
5
6
7
8
6
7
8
1
2
GND
SDA
SCL
V
BAT
V
DD
Ordering Information
PART
NUMBER
(Notes 1, 2, 3)
ISL12027IB27Z
ISL12027IB27AZ
ISL12027IB30AZ
ISL12027IBZ
ISL12027IBAZ
ISL12027IV27Z
ISL12027IV27AZ
ISL12027IV30AZ
PART
MARKING
12027 IB27Z
12027 IB27AZ
12027 IB30AZ
12027 IBZ
12027 IBAZ
2027 I27Z
2027 27AZ
2027 30AZ
V
BAT
TRIP POINT
(V)
V
DD
< V
BAT
V
DD
< V
BAT
V
DD
< V
BAT
V
DD
< V
BAT
V
DD
< V
BAT
V
DD
< V
BAT
V
DD
< V
BAT
V
DD
< V
BAT
V
DD
< V
BAT
BSW BIT DEFAULT
SETTING
BSW = 1
BSW = 1
BSW = 1
BSW = 1
BSW = 1
BSW = 1
BSW = 1
BSW = 1
BSW = 1
V
RESET
VOLTAGE
(V)
2.63
2.92
3.09
4.38
4.64
2.63
2.92
3.09
4.38
TEMP. RANGE
(°C)
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
PACKAGE
(Pb-Free)
8 Ld SOIC
8 Ld SOIC
8 Ld SOIC
8 Ld SOIC
8 Ld SOIC
8 Ld TSSOP
8 Ld TSSOP
8 Ld TSSOP
8 Ld TSSOP
PKG.
DWG. #
M8.15
M8.15
M8.15
M8.15
M8.15
M8.173
M8.173
M8.173
M8.173
2027 IVZ
ISL12027IVZ
(No
longer available or
supported)
ISL12027IVAZ
(No
2027 IVAZ
longer available or
supported)
12027A IB27Z
ISL12027AIB27Z
(No longer available
or supported)
2027A I27Z
ISL12027AIV27Z
(No longer available
or supported)
NOTES:
V
DD
< V
BAT
BSW = 1
4.64
-40 to +85
8 Ld TSSOP
M8.173
V
DD
< V
BAT
BSW = 0
2.63
-40 to +85
8 Ld SOIC
M8.15
V
DD
< V
BAT
BSW =0
2.63
-40 to +85
8 Ld TSSOP
M8.173
1. Add “-T” suffix for tape and reel. Please refer to
TB347
for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-
020.
3. For Moisture Sensitivity Level (MSL), please see device information page for
ISL12027, ISL12027A.
For more information on MSL please see
techbrief
TB363.
FN8232 Rev 9.00
September 23, 2015
Page 2 of 29
ISL12027, ISL12027A
Block Diagram
OSC COMPENSATION
32.768kHZ
X1
X2
OSCILLATOR
TIMER
FREQUENCY 1Hz CALENDAR
DIVIDER
LOGIC
TIME
KEEPING
REGISTERS
(SRAM)
BATTERY
SWITCH
CIRCUITRY
V
DD
V
BAT
SCL
SDA
MASK
CONTROL
SERIAL
INTERFACE DECODE
LOGIC
DECODER
8
RESET
CONTROL/
REGISTERS
(EEPROM)
STATUS
REGISTERS
(SRAM)
ALARM
COMPARE
ALARM REGS
(EEPROM)
4k
EEPROM
ARRAY
WATCHDOG
TIMER
LOW VOLTAGE
RESET
FN8232 Rev 9.00
September 23, 2015
Page 3 of 29
ISL12027, ISL12027A
Absolute Maximum Ratings
Voltage on V
DD
, V
BAT
, SCL, SDA, and RESET pins
(respect to ground) . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6.0V
Voltage on X1 and X2 pins
(respect to ground) . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 2.5V
Latchup (Note 4) . . . . . . . . . . . . . . . . . . . Class II, Level B @ +85°C
ESD Rating
Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±2kV
Machine Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .175V
Thermal Information
Thermal Resistance (Typical)
JA
(°C/W)
JC
(°C/W)
8 Ld SOIC Package (Notes 5, 6) . . . . .
115
50
8 Ld TSSOP Package (Notes 5, 6) . . .
140
40
Maximum Junction Temperature (Plastic Package) . . . . . . . +150°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTES:
4. Jedec Class II pulse conditions and failure criterion used. Level B exceptions are: Using a max positive pulse of 8.35V on all pins except X1 and
X2, Using a max positive pulse of 2.75V on X1 and X2, and using a max negative pulse of -1V for all pins.
5.
JA
is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
6. For
JC
, the “case temp” location is taken at the package top center.
DC Electrical Specifications
Unless otherwise noted, V
DD
= +2.7V to +5.5V, T
A
= -40°C to +85°C, Typical values are at T
A
= +25°C and
V
DD
= 3.3V.
Boldface limits apply over the operating temperature range, -40°C to +85°C.
CONDITIONS
MIN
(Note 16)
2.7
1.8
TYP
MAX
(Note 16)
5.5
5.5
UNIT
V
V
NOTES
SYMBOL
V
DD
V
BAT
PARAMETER
Main Power Supply
Backup Power Supply
Electrical Specifications
SYMBOL
I
DD1
Boldface limits apply over the operating temperature range, -40°C to +85°C.
CONDITIONS
V
DD
= 2.7V
V
DD
= 5.5V
MIN
(Note 16)
TYP
MAX
(Note 16)
500
800
2.5
3.5
10
20
800
850
-100
1.8
2.2
30
50
10
1000
1200
100
2.6
UNIT
µA
µA
mA
mA
µA
µA
nA
nA
nA
V
mV
mV
V/ms
11
11, 14
11, 14
12
7, 10, 11
9
7, 8, 9
NOTES
7, 8, 9
PARAMETER
Supply Current with I
2
C Active
I
DD2
Supply Current for Non-Volatile
Programming
Supply Current for Main
Timekeeping (Low Power Mode)
Battery Supply Current
V
DD
= 2.7V
V
DD
= 5.5V
V
DD
= V
SDA
= V
SCL
= 2.7V
V
DD
= V
SDA
= V
SCL
= 5.5V
V
BAT
= 1.8V,
V
DD
= V
SDA
= V
SCL
= V
RESET
= 0V
V
BAT
= 3.0V,
V
DD
= V
SDA
= V
SCL
= V
RESET
= 0V
I
DD3
I
BAT
I
BATLKG
V
TRIP
Battery Input Leakage
V
BAT
Mode Threshold
V
DD
= 5.5V, V
BAT
= 1.8V
V
TRIPHYS
V
TRIP
Hysteresis
V
BATHYS
V
DD SR-
V
BAT
Hysteresis
V
DD
Negative Slew rate
RESET OUTPUT
V
OL
Output Low Voltage
V
DD
= 5.5V
I
OL
= 3mA
V
DD
= 2.7V
I
OL
= 1mA
I
LO
Output Leakage Current
V
DD
= 5.5V
V
OUT
= 5.5V
100
0.4
0.4
400
V
V
nA
FN8232 Rev 9.00
September 23, 2015
Page 4 of 29
ISL12027, ISL12027A
Watchdog Timer/Low Voltage Reset Parameters
SYMBOL
t
RPD
t
PURST
V
RVALID
V
RESET
PARAMETER
V
DD
Detect to RESET LOW
Power-up Reset Time-Out Delay
Minimum V
DD
for Valid RESET
Output
ISL12027-4.5A Reset Voltage Level
ISL12027 Reset Voltage Level
ISL12027-3 Reset Voltage Level
ISL12027-2.7A Reset Voltage Level
ISL12027-2.7 Reset Voltage Level
t
WDO
Watchdog Timer Period
32.768kHz crystal between X1
and X2
100
1.0
4.59
4.33
3.04
2.87
2.58
1.70
725
225
t
RST
t
RSP
Watchdog Timer Reset Time-Out
Delay
I
2
C Interface Minimum Restart Time
32.768kHz crystal between X1
and X2
225
1.2
4.64
4.38
3.09
2.92
2.63
1.75
750
250
250
4.69
4.43
3.14
2.97
2.68
1.801
775
275
275
CONDITIONS
MIN
(Note 16)
TYP
(Note 5)
500
250
400
MA
(Note 16)
UNITS
ns
ms
V
V
V
V
V
V
s
ms
ms
ms
µs
NOTES
13
EEPROM SPECIFICATIONS
EEPROM Endurance
EEPROM Retention
Temperature
75°C
>2,000,000
50
Cycles
Years
Serial Interface (I
2
C) Specifications
SYMBOL
V
IL
V
IH
PARAMETER
SDA, and SCL Input Buffer LOW
Voltage
SDA, and SCL Input Buffer HIGH
Voltage
CONDITIONS
SBIB = 1 (Under V
DD
mode)
SBIB = 1 (Under V
DD
mode)
SBIB = 1 (Under V
DD
mode)
I
OL
= 4mA
V
IN
= 5.5V
V
IN
= 5.5V
MIN
-0.3
0.7xV
DD
0.05xV
DD
0
0.1
0.1
0.4
10
10
TYP
MAX
0.3xV
DD
V
DD
+ 0.3
UNITS
V
V
V
V
µA
µA
NOTES
Hysteresis SDA and SCL Input Buffer
Hysteresis
V
OL
I
LI
I
LO
SDA Output Buffer LOW Voltage
Input Leakage Current on SCL
I/O Leakage Current on SDA
TIMING CHARACTERISTICS
f
SCL
t
IN
t
AA
SCL Frequency
Pulse Width Suppression Time at
SDA and SCL Inputs
SCL Falling Edge to SDA Output
Data Valid
Time the Bus Must be Free Before
the Start of a New Transmission
Any pulse narrower than the max spec
is suppressed.
SCL falling edge crossing 30% of V
DD
,
until SDA exits the 30% to 70% of V
DD
window.
SDA crossing 70% of V
DD
during a
STOP condition, to SDA crossing 70%
of V
DD
during the following START
condition.
Measured at the 30% of V
DD
crossing.
Measured at the 70% of V
DD
crossing.
1300
400
50
900
kHz
ns
ns
t
BUF
ns
t
LOW
t
HIGH
Clock LOW Time
Clock HIGH Time
1300
600
ns
ns
FN8232 Rev 9.00
September 23, 2015
Page 5 of 29
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