All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner.
The information furnished in this publication is
PRELIMINARY
and subject to changes without notice.
ZADCS146/147
12-Bit, 200ksps, ADC Family
Typical Applications
Embedded control & real time appl.
Industrial control & process control
ZADCS146 Block Diagram
applications
Motion control applications
Three phase motor control
Power generation (Solar,
Windmills, etc.)
Data Acquisition
Portable Data Logging
Battery-Powered Systems
Automotive
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
COM
IN -
SAR
8-Channel
Analog
Input
Multiplexer
Comparator
IN +
DAC
with inherent
T&H
+
-
+1.25V
Reference
REFADJ
VREF
x 2.00
Serial
Interface
and
Control
State
Machine
nCS
SCLK
DIN
DOUT
SSTRB
nSHDN
Internal
3.2 MHz
Oscillator
VDD
DGND
AGND
Available in ZADCS146
Ordering Information
Temperature
range
[°C]
Sample Rate
[ksps]
Channels
[number]
Pins
[number]
Package
[Type]
SSOP
SSOP
ZADCS146VIS20T
ZADCS147IS20T
12
12
8
8
200
200
-25°C to +85°C
-25°C to +85°C
--
± 1 LSB
± 1 LSB
± 1 LSB
± 1 LSB
20
20
Tube
Tube
Sales and Further Information
Zentrum Mikroelektronik
Dresden AG
Grenzstrasse 28
01109 Dresden
Germany
Phone
Fax
+49 (0)351.8822.7232
+49 (0)351.8822.87232
www.zmdi.com
Zentrum Mikroelektronik
Dresden AG, Japan Office
2nd Floor, Shinbashi Tokyu Bldg.
4-21-3, Shinbashi, Minato-ku
Tokyo, 105-0004
Japan
Phone
Fax
+81.3.6895.7410
+81.3.6895.7301
adc@zmdi.com
ZMD FAR EAST, Ltd.
3F, No. 51, Sec. 2,
Keelung Road
11052 Taipei
Taiwan
Phone
Fax
+886 2 2377 8189
+886 2 2377 8199
ZMD America, Inc.
8413 Excelsior Drive
Suite 200
Madison, WI 53717
USA
Phone
Fax
+1 (608) 829-1987
+1 (631) 549-2882
DISCLAIMER: This information applies to a product under development. Its characteristics and specifications are
PRELIMINARY
and subject to change without notice. Zentrum
Mikroelektronik Dresden AG (ZMD AG) assumes no obligation regarding future manufacture unless otherwise agreed to in writing. The information furnished hereby is believed to be
true and accurate. However, under no circumstances shall ZMD AG be liable to any customer, licensee, or any other third party for any special, indirect, incidental, or consequential
damages of any kind or nature whatsoever arising out of or in any way related to the furnishing, performance, or use of this technical data. ZMD AG hereby expressly disclaims any
liability of ZMD AG to any customer, licensee or any other third party, and any such customer, licensee and any other third party hereby waives any liability of ZMD AG for any
damages in connection with or arising out of the furnishing, performance or use of this technical data, whether based on contract, warranty, tort (including negligence), strict liability, or
All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner.
The information furnished in this publication is
PRELIMINARY
and subject to changes without notice.
Packing
Order Code
Internal Vref
Resolution
[Bit]
DNL
INL
ZADCS146/147
12-Bit, 200ksps, ADC Family
Contents
1
GENERAL DEVICE SPECIFICATION ................................................................................................................................. 7
1.1.
1.2.
1.3.
ABSOLUTE MAXIMUM RATINGS (NON OPERATING) ............................................................................................. 7
GENERAL PARAMETERS ................................................................................................................................... 9
SPECIFIC PARAMETERS OF ZADCS146 VERSIONS ..................................................................................... 10
SPECIFIC PARAMETERS OF BASIC ZADCS147 VERSIONS ......................................................................... 11
DIGITAL PIN PARAMETERS ............................................................................................................................. 11
GENERAL OPERATION ............................................................................................................................................ 14
ANALOG INPUT......................................................................................................................................................... 15
DIGITAL INTERFACE ................................................................................................................................................ 17
2.5.
POWER DISSIPATION .............................................................................................................................................. 21
All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without
the prior written consent of the copyright owner. The information furnished in this publication is
PRELIMINARY
and subject to
changes without notice.
4 of 25
ZADCS146/147
12-Bit, 200ksps, ADC Family
List of Figures
Figure 1 Package Pin Assignment for ZADCS146 & ZADCS147 ..............................................................................8
Figure 2: Basic application schematic for ZADCS146..............................................................................................14
Figure 3: Basic application schematic for ZADCS147..............................................................................................14
Figure 4: Input voltage range in unipolar mode ........................................................................................................15
Figure 5: Input voltage range for bipolar mode ........................................................................................................15
Figure 6: Block diagram of input multiplexer ............................................................................................................16
Figure 7: Equivalent input circuit during sampling....................................................................................................16
Figure 14: Unipolar Transfer Function......................................................................................................................21
Figure 15: Bipolar Transfer Function ........................................................................................................................21
Figure 16: Supply Current versus Sampling Rate ....................................................................................................23
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FPGA/CPLD
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