DS21610N datasheet, PDF - EEWORLD Datasheet

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DS21610N: DescriptionPLL Based Clock Driver, 2 True Output(s), 0 Inverted Output(s), PDIP8, DIP-8; Categorylogic logic; File Size56KB，13 Pages; ManufacturerMaxim; Websitehttps://www.maximintegrated.com/en.html

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DS21610N Overview

PLL Based Clock Driver, 2 True Output(s), 0 Inverted Output(s), PDIP8, DIP-8

DS21610N Parametric

Parameter Name	Attribute value
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Maker	Maxim
Parts packaging code	DIP
package instruction	DIP,
Contacts	8
Reach Compliance Code	compliant
Input adjustment	STANDARD
JESD-30 code	R-PDIP-T8
JESD-609 code	e0
length	9.375 mm
Logic integrated circuit type	PLL BASED CLOCK DRIVER
Number of functions	1
Number of inverted outputs
Number of terminals	8
Actual output times	2
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Package body material	PLASTIC/EPOXY
encapsulated code	DIP
Package shape	RECTANGULAR
Package form	IN-LINE
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
Certification status	Not Qualified
Maximum seat height	4.572 mm
Maximum supply voltage (Vsup)	5.25 V
Minimum supply voltage (Vsup)	4.75 V
Nominal supply voltage (Vsup)	5 V
surface mount	NO
Temperature level	INDUSTRIAL
Terminal surface	TIN LEAD
Terminal form	THROUGH-HOLE
Terminal pitch	2.54 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED
width	7.62 mm

DS21610N Preview

Preliminary

DS21610

Clock Rate Adapter

www.dalsemi.com

FEATURES

•

Direct replacement for LXP610SE

Converts E-carrier clock rates to T-carrier

clock rates

Converts T-carrier clock rates to E-carrier

clock rates

Low output jitter

Multiple output clocks synchronized to input

clock

8kHz frequency locked output for all modes

of operation

No external components required

16-pin SOIC

Industrial temperature range

DALLAS

DS21610

ORDERING INFORMATION

DS21610SN 16–pin SOIC (–40°C to +85°C)

DS21610N

8-pin DIP

(–40°C to +85°C)

DS21610QN 28-pin PLCC (–40°C to +85°C)

DESCRIPTION

The DS21610 is a multi-rate, low jitter, clock adapter which converts E-carrier and T-carrier clocks to

multiple PDH carrier clock rates. Two clock outputs are available which are frequency locked to the

input clock. The clock outputs along with an 8 kHz frame sync output can be phased aligned to a frame

sync input. The device is backward compatible to the LXP610 and operates from a single 5V supply. All

modes of operation include a standard 8 kHz output.

Page 1 of 13

013101

DS21610

TABLE OF CONTENTS

1. REVISION HISTORY............................................................................................... 4

2. FUNCTIONAL DESCRIPTION .............................................................................. 5

2.1 P

UNCTION

ESCRIPTION

................................................................................... 6

2.2 C

OMPATIBLITY

LXP610SE ............................................................................... 8

3. OPERATION.............................................................................................................. 9

4. JITTER SPECIFICATIONS................................................................................... 10

5. OPERATING PARAMETERS............................................................................... 11

5.1 T

IMING

.................................................................................................................. 12

6. PACKAGE SPECIFICATIONS ............................................................................. 13

Page 2 of 13

DS21610

LIST OF TABLES

Table 2-1 PIN DESCRIPTION SORTED BY PIN NUMBER........................................... 7

Table 2-2 PIN NAME CROSS REFERENCE TO LXP610SE .......................................... 8

Table 3-1 PROGRAM PIN FUNCTIONS (SEL = 0)......................................................... 9

Table 3-2 PROGRAM PIN FUNCTIONS (SEL = 1)......................................................... 9

Table 4-1 OUTPUT JITTER SPECIFICATIONS, CLKOUT1 = 1.544 MHz.................. 10

Table 4-2 OUTPUT JITTER SPECIFICATIONS, CLKOUT1 = 2.048 MHz.................. 10

Table 5-1 AC TIMING ..................................................................................................... 12

LIST OF FIGURES

Figure 2-1 BLOCK DIAGRAM OF THE DS21610........................................................... 5

Figure 4-1 NOMINAL JITTER TRANSFER (1.544 MHz CLKIN TO 2.048 MHz CLKOUT1)

Figure 4-2 NOMINAL JITTER TRANSFER (1.544 MHz CLKIN TO 2.048 MHz CLKOUT1)

Figure 6-1 PACKAGE OUTLINE SOIC 16 PIN 0.300” BODY.................................... 13+

Page 3 of 13

DS21610

REVISION HISTORY

COMMENTS

Preliminary release

Remove references to 3 volt operation

Add FSP pin to block diagram

DATE

9-01-00

11-27-00

12-06-00

Page 4 of 13

DS21610

FUNCTIONAL DESCRIPTION

A clock input at CLKIN is converted to various clocks available on CLKOUT1 and CLKOUT2.

Additionally, an 8 kHz clock locked to CLKIN and SYNCIN (if present) is always available at the

SYNCOUT pin. The pulse width of the SYNCOUT, is selectable. It can be one or one half the clock

period of CLKIN, centered on the rising edge of CLKIN. Pins P1 through P4 are used to select the

various clock rates and operational modes. Table 3-1 and Table 3-2 list the various operational modes of

the DS21610.

CLKIN, CLKOUT1 and CLOCKOUT2 are always frequency locked. They can all be phase locked to a

system frame sync pulse. A frame sync pulse applied to SYNCIN will cause CLKIN and CLKOUT1 and

CLKOUT2 to be phased locked to that sync pulse. This will cause the clocks to have a fixed alignment at

the frame sync boundries. The signal applied to SYNCIN can be 8 kHz or some integer sub-rate such as

1, 2 or 4 kHz. Phase synchronization will occur within a maximum of 500ms when SYNCIN is 8 kHz.

FIGURE 2-1 BLOCK DIAGRAM OF THE DS21610

CLKOUT2

CLKIN

ANALOG

PLL

FEEDBACK

CIRCUIT

OUTPUT

DIVIDER

CLKOUT1

SEL

SYNCIN

FRAME SYNC

GENERATOR

SYNCOUT

FSP

FREQUENCY

PLL

SELECT

LOGIC

Page 5 of 13

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DS21610N Related Products

	DS21610N
Description	PLL Based Clock Driver, 2 True Output(s), 0 Inverted Output(s), PDIP8, DIP-8
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Maker	Maxim
Parts packaging code	DIP
package instruction	DIP,
Contacts	8
Reach Compliance Code	compliant
Input adjustment	STANDARD
JESD-30 code	R-PDIP-T8
JESD-609 code	e0
length	9.375 mm
Logic integrated circuit type	PLL BASED CLOCK DRIVER
Number of functions	1
Number of terminals	8
Actual output times	2
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Package body material	PLASTIC/EPOXY
encapsulated code	DIP
Package shape	RECTANGULAR
Package form	IN-LINE
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
Certification status	Not Qualified
Maximum seat height	4.572 mm
Maximum supply voltage (Vsup)	5.25 V
Minimum supply voltage (Vsup)	4.75 V
Nominal supply voltage (Vsup)	5 V
surface mount	NO
Temperature level	INDUSTRIAL
Terminal surface	TIN LEAD
Terminal form	THROUGH-HOLE
Terminal pitch	2.54 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED
width	7.62 mm

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