Data Sheet
FEATURES
Octal, 14-Bit, 125 MSPS, Serial LVDS,
1.8 V Analog-to-Digital Converter
AD9681
SIMPLIFIED FUNCTIONAL BLOCK DIAGRAM
AVDD
PDWN
DRVDD
SERIAL
LVDS
DIGITAL
SERIALIZER
14
SDIO/OLM
SCLK/DTP
RBIAS1, RBIAS2
Medical imaging
Communications receivers
Multichannel data acquisition
Figure 1.
GENERAL DESCRIPTION
The
AD9681
is an octal, 14-bit, 125 MSPS analog-to-digital
converter (ADC) with an on-chip sample-and-hold circuit that
is designed for low cost, low power, small size, and ease of use.
The device operates at a conversion rate of up to 125 MSPS and
is optimized for outstanding dynamic performance and low
power in applications where a small package size is critical.
The ADC requires a single 1.8 V power supply and an LVPECL-/
CMOS-/LVDS-compatible sample rate clock for full performance
operation. No external reference or driver components are
required for many applications.
The
AD9681
automatically multiplies the sample rate clock for
the appropriate LVDS serial data rate. Data clock outputs (DCO±1,
DCO±2) for capturing data on the output and frame clock outputs
(FCO±1, FCO±2) for signaling a new output byte are provided.
Individual channel power-down is supported, and the device
typically consumes less than 2 mW when all channels are disabled.
The ADC contains several features designed to maximize flexibility
and minimize system cost, such as programmable clock and data
alignment and programmable digital test pattern generation. The
available digital test patterns include built-in deterministic and
pseudorandom patterns, along with custom user-defined test
patterns entered via the serial port interface (SPI).
The
AD9681
is available in an RoHS-compliant, 144-ball
CSP-BGA. It is specified over the industrial temperature range of
−40°C to +85°C. This product is protected by a U.S. patent.
PRODUCT HIGHLIGHTS
1.
2.
3.
Small Footprint. Eight ADCs are contained in a small,
10 mm × 10 mm package.
Low Power. The device dissipates 110 mW per channel at
125 MSPS with scalable power options.
Ease of Use. Data clock outputs (DCO±1, DCO±2) operate
at frequencies of up to 500 MHz and support double data
rate (DDR) operation.
User Flexibility. SPI control offers a wide range of flexible
features to meet specific system requirements.
4.
Rev. C
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11537-200
APPLICATIONS
CSB1, CSB2
SYNC
Low power
8 ADC channels integrated into 1 package
110 mW per channel at 125 MSPS with scalable power
options
SNR: 74 dBFS (to Nyquist); SFDR: 90 dBc (to Nyquist)
DNL: ±0.8 LSB (typical); INL: ±1.2 LSB (typical)
Crosstalk, worst adjacent channel, 70 MHz, −1 dBFS: −83 dB
typical
Serial LVDS (ANSI-644, default)
Low power, reduced signal option (similar to IEEE 1596.3)
Data and frame clock outputs
650 MHz full power analog bandwidth
2 V p-p input voltage range
1.8 V supply operation
Serial port control
Flexible bit orientation
Built-in and custom digital test pattern generation
Programmable clock and data alignment
Power-down and standby modes
AD9681
VIN+A1
VIN–A1
VIN+A2
VIN–A2
14
PIPELINE
ADC
PIPELINE
ADC
SERIAL
LVDS
SERIAL
LVDS
SERIAL
LVDS
DIGITAL
SERIALIZER
D0+A1
D0–A1
D1+A1
D1–A1
D0+A2
D0–A2
D1+A2
D1–A2
VIN+D1
VIN–D1
VIN+D2
VIN–D2
VREF
SENSE
VCM1, VCM2
GND
14
PIPELINE
ADC
14
DIGITAL
SERIALIZER
DIGITAL
SERIALIZER
SERIAL
LVDS
SERIAL
LVDS
SERIAL
LVDS
SERIAL
LVDS
PIPELINE
ADC
REF
SELECT
1V
D0+D1
D0–D1
D1+D1
D1–D1
D0+D2
D0–D2
D1+D2
D1–D2
FCO+1, FCO+2
FCO–1, FCO–2
SERIAL PORT
INTERFACE
CLOCK
MANAGEMENT
CLK+
CLK–
DCO+1, DCO+2
DCO–1, DCO–2
AD9681
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Simplified Functional Block Diagram ........................................... 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 2
Functional Block Diagram .............................................................. 3
Specifications..................................................................................... 4
DC Specifications ......................................................................... 4
AC Specifications.......................................................................... 5
Digital Specifications ................................................................... 6
Switching Specifications .............................................................. 7
Timing Specifications .................................................................. 8
Absolute Maximum Ratings.......................................................... 12
Thermal Characteristics ............................................................ 12
ESD Caution ................................................................................ 12
Pin Configuration and Function Descriptions ........................... 13
Typical Performance Characteristics ........................................... 16
Equivalent Circuits ......................................................................... 19
Theory of Operation ...................................................................... 20
Analog Input Considerations.................................................... 20
Voltage Reference ....................................................................... 21
Clock Input Considerations ...................................................... 22
Data Sheet
Power Dissipation and Power-Down Mode ........................... 24
Digital Outputs and Timing ..................................................... 25
Output Test Modes ..................................................................... 28
Serial Port Interface (SPI) .............................................................. 29
Configuration Using the SPI ..................................................... 29
Hardware Interface..................................................................... 30
Configuration Without the SPI ................................................ 30
SPI Accessible Features .............................................................. 30
Memory Map .................................................................................. 31
Reading the Memory Map Register Table............................... 31
Memory Map .............................................................................. 32
Memory Map Register Descriptions ........................................ 35
Applications Information .............................................................. 38
Design Guidelines ...................................................................... 38
Power and Ground Recommendations ................................... 38
Board Layout Considerations ................................................... 38
Clock Stability Considerations ................................................. 39
VCM ............................................................................................. 39
Reference Decoupling ................................................................ 39
SPI Port ........................................................................................ 39
Outline Dimensions ....................................................................... 40
Ordering Guide .......................................................................... 40
REVISION HISTORY
10/15—Rev. B to Rev. C
Added Endnote 4, Table 4; Renumbered Sequentially ................ 7
Changes to Clock Input Options Section .................................... 23
Changes to Digital Outputs and Timing Section ....................... 27
2/15—Rev. A to Rev. B
Changes to SYNC Timing Requirements Parameter, Table 5 .... 8
Changes to Figure 7 ........................................................................ 10
Changes to Figure 8 ........................................................................ 11
Changes to Table 8 .......................................................................... 13
Changed AD9515-x to AD9515 ................................................... 23
Changes to Digital Outputs and Timing Section and Table 11 ..... 27
12/13—Rev. 0 to Rev. A
Changes to Ordering Guide .......................................................... 39
11/13—Revision 0: Initial Version
Rev. C | Page 2 of 40
Data Sheet
FUNCTIONAL BLOCK DIAGRAM
AVDD
PDWN
DRVDD
SERIAL
LVDS
DIGITAL
SERIALIZER
14
AD9681
AD9681
VIN+A1
VIN–A1
VIN+A2
VIN–A2
VIN+B1
VIN–B1
VIN+B2
VIN–B2
RBIAS1, RBIAS2
VREF
SENSE
REF
SELECT
GND
14
14
PIPELINE
ADC
PIPELINE
ADC
14
SERIAL
LVDS
SERIAL
LVDS
SERIAL
LVDS
SERIAL
LVDS
SERIAL
LVDS
SERIAL
LVDS
SERIAL
LVDS
DIGITAL
SERIALIZER
DIGITAL
SERIALIZER
14
PIPELINE
ADC
PIPELINE
ADC
DIGITAL
SERIALIZER
D0+A1
D0–A1
D1+A1
D1–A1
D0+A2
D0–A2
D1+A2
D1–A2
D0+B1
D0–B1
D1+B1
D1–B1
D0+B2
D0–B2
D1+B2
D1–B2
FCO+1, FCO+2
FCO–1, FCO–2
1V
SERIAL
LVDS
DIGITAL
SERIALIZER
14
VIN+C1
VIN–C1
VIN+C2
VIN–C2
VIN+D1
VIN–D1
VIN+D2
VIN–D2
VCM1, VCM2
PIPELINE
ADC
PIPELINE
ADC
14
SERIAL
LVDS
SERIAL
LVDS
SERIAL
LVDS
SERIAL
LVDS
SERIAL
LVDS
SERIAL
LVDS
SERIAL
LVDS
DIGITAL
SERIALIZER
DIGITAL
SERIALIZER
14
PIPELINE
ADC
PIPELINE
ADC
DIGITAL
SERIALIZER
D0+C1
D0–C1
D1+C1
D1–C1
D0+C2
D0–C2
D1+C2
D1–C2
D0+D1
D0–D1
D1+D1
D1–D1
D0+D2
D0–D2
D1+D2
D1–D2
DCO+1, DCO+2
DCO–1, DCO–2
SERIAL PORT
INTERFACE
CLOCK
MANAGEMENT
SDIO/OLM
SCLK/DTP
CSB1, CSB2
SYNC
CLK+
CLK–
Figure 2.
Rev. C | Page 3 of 40
11537-001
AD9681
SPECIFICATIONS
DC SPECIFICATIONS
Data Sheet
AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, A
IN
= −1.0 dBFS, unless otherwise noted.
Table 1.
Parameter
1
RESOLUTION
ACCURACY
No Missing Codes
Offset Error
Offset Matching
Gain Error
Gain Matching
Differential Nonlinearity (DNL)
Integral Nonlinearity (INL)
TEMPERATURE DRIFT
Offset Error
Gain Error
INTERNAL VOLTAGE REFERENCE
Output Voltage (1 V Mode)
Load Regulation at 1.0 mA (V
REF
= 1 V)
Input Resistance
INPUT-REFERRED NOISE
V
REF
= 1.0 V
ANALOG INPUTS
Differential Input Voltage (V
REF
= 1 V)
Common-Mode Voltage
Differential Input Resistance
Differential Input Capacitance
POWER SUPPLY
AVDD
DRVDD
I
AVDD
I
DRVDD
(ANSI-644 Mode)
I
DRVDD
(Reduced Range Mode)
TOTAL POWER CONSUMPTION
Total Power Dissipation (Eight Channels, Including Output Drivers
ANSI-644 Mode)
Total Power Dissipation (Eight Channels, Including Output Drivers
Reduced Range Mode)
Power-Down Dissipation
Standby Dissipation
2
1
2
Temp
Min
14
Typ
Max
Unit
Bits
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
25°C
Full
25°C
Full
Full
Full
Full
Full
Full
Full
Full
25°C
Full
25°C
25°C
25°C
−0.23
0
−8.0
0
−0.92
−4.0
Guaranteed
+0.21
0.24
−3.1
1.8
±0.8
±1.2
−4
38
+0.62
0.7
+1.7
6.0
+1.75
+4.0
% FSR
% FSR
% FSR
% FSR
LSB
LSB
ppm/°C
ppm/°C
0.98
1.0
3
7.5
0.99
2
0.9
5.2
3.5
1.8
1.8
368
120
90
879
825
2
485
1.02
V
mV
kΩ
LSB rms
V p-p
V
kΩ
pF
V
V
mA
mA
mA
mW
mW
mW
mW
0.5
1.3
1.7
1.7
1.9
1.9
423
126
988
See the
AN-835 Application Note,
Understanding High Speed ADC Testing and Evaluation,
for definitions and for information about how these tests were completed.
Controlled via the SPI.
Rev. C | Page 4 of 40
Data Sheet
AC SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, A
IN
= −1.0 dBFS, unless otherwise noted.
Table 2.
Parameter
1
SIGNAL-TO-NOISE RATIO (SNR)
f
IN
= 9.7 MHz
f
IN
= 19.7 MHz
f
IN
= 69.5 MHz
f
IN
= 139.5 MHz
f
IN
= 201 MHz
f
IN
= 301 MHz
SIGNAL-TO-NOISE AND DISTORTION RATIO (SINAD)
f
IN
= 9.7 MHz
f
IN
= 19.7 MHz
f
IN
= 69.5 MHz
f
IN
= 139.5 MHz
f
IN
= 201 MHz
f
IN
= 301 MHz
EFFECTIVE NUMBER OF BITS (ENOB)
f
IN
= 9.7 MHz
f
IN
= 19.7 MHz
f
IN
= 69.5 MHz
f
IN
= 139.5 MHz
f
IN
= 201 MHz
f
IN
= 301 MHz
SPURIOUS-FREE DYNAMIC RANGE (SFDR)
f
IN
= 9.7 MHz
f
IN
= 19.7 MHz
f
IN
= 69.5 MHz
f
IN
= 139.5 MHz
f
IN
= 201 MHz
f
IN
= 301 MHz
WORST HARMONIC (SECOND OR THIRD)
f
IN
= 9.7 MHz
f
IN
= 19.7 MHz
f
IN
= 69.5 MHz
f
IN
= 139.5 MHz
f
IN
= 201 MHz
f
IN
= 301 MHz
WORST OTHER (EXCLUDING SECOND OR THIRD)
f
IN
= 9.7 MHz
f
IN
= 19.7 MHz
f
IN
= 69.5 MHz
f
IN
= 139.5 MHz
f
IN
= 201 MHz
f
IN
= 301 MHz
TWO-TONE INTERMODULATION DISTORTION (IMD)—AIN1 AND AIN2 = −7.0 dBFS
f
IN1
= 70 MHz, f
IN2
= 72.5 MHz
CROSSTALK, WORST ADJACENT CHANNEL
2
Crosstalk, Worst Adjacent Channel Overrange Condition
3
ANALOG INPUT BANDWIDTH, FULL POWER
1
2
AD9681
Temp
25°C
25°C
Full
25°C
25°C
25°C
25°C
25°C
Full
25°C
25°C
25°C
25°C
25°C
Full
25°C
25°C
25°C
25°C
25°C
Full
25°C
25°C
25°C
25°C
25°C
Full
25°C
25°C
25°C
25°C
25°C
Full
25°C
25°C
25°C
25°C
25°C
25°C
25°C
Min
Typ
74.8
74.7
73.9
71.5
69.6
66.6
74.7
74.7
73.8
71.4
69.3
65.8
12.1
12.1
12.0
11.6
11.2
10.6
94
94
90
87
83
73
−94
−94
−90
−87
−83
−73
−98
−94
−96
−90
−85
−75
94
−83
−79
650
Max
Unit
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
Bits
Bits
Bits
Bits
Bits
Bits
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dB
dB
MHz
72.6
72.3
11.7
81
−81
−84
See the
AN-835 Application Note,
Understanding High Speed ADC Testing and Evaluation,
for definitions and for details on how these tests were completed.
Crosstalk is measured at 70 MHz, with −1.0 dBFS analog input on one channel and no input on the adjacent channel.
3
Overrange condition is defined as 3 dB above input full scale.
Rev. C | Page 5 of 40
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