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PUMA2E1000I-15

Description
EEPROM Module, 32KX32, 150ns, Parallel, CMOS, CPGA66, CERAMIC, PGA-66
Categorystorage    storage   
File Size107KB,2 Pages
ManufacturerAPTA Group Inc
Download Datasheet Parametric View All

PUMA2E1000I-15 Overview

EEPROM Module, 32KX32, 150ns, Parallel, CMOS, CPGA66, CERAMIC, PGA-66

PUMA2E1000I-15 Parametric

Parameter NameAttribute value
MakerAPTA Group Inc
Parts packaging codePGA
package instructionPGA, PGA66,11X11
Contacts66
Reach Compliance Codeunknown
ECCN codeEAR99
Maximum access time150 ns
Other featuresUSER CONFIGURABLE AS 128K X 8
Spare memory width16
Data pollingYES
JESD-30 codeS-CPGA-P66
memory density1048576 bit
Memory IC TypeEEPROM MODULE
memory width32
Number of functions1
Number of terminals66
word count32768 words
character code32000
Operating modeASYNCHRONOUS
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
organize32KX32
Package body materialCERAMIC, METAL-SEALED COFIRED
encapsulated codePGA
Encapsulate equivalent codePGA66,11X11
Package shapeSQUARE
Package formGRID ARRAY
page size64 words
Parallel/SerialPARALLEL
power supply5 V
Programming voltage5 V
Certification statusNot Qualified
Maximum seat height8.13 mm
Maximum standby current0.0012 A
Maximum slew rate0.32 mA
Nominal supply voltage (Vsup)5 V
surface mountNO
technologyCMOS
Temperature levelINDUSTRIAL
Terminal formPIN/PEG
Terminal pitch2.54 mm
Terminal locationPERPENDICULAR
switch bitYES
typeNOR TYPE
write protectSOFTWARE
TRAILING EDGE PRODUCT - MINIMUM ORDER APPLIES.
PRODUCT MAY BE MADE OBSOLETE WITHOUT NOTICE
32K x 32 EEPROM MODULE
EEPROM
PUMA 2E1000 - 150/200/250
Issue 4.1 : May 2001
Description
The PUMA 2E1000 is a 1Mbit EEPROM
module user configurable as 32Kx32,
64Kx16 or 128Kx8. Available with access
times of 150, 200 & 250ns the device has an
industry standard ceramic 66 pin P.G.A
footprint.
The device features byte and page write
facility, 10,000 Write Erase cycle capability
and data retention time of 10 years.
The device may be screened in accordance
with MIL-STD-883
1,048,576 bit CMOS High Speed EEPROM
Features
Access times of 150/200/250 ns.
User Configurable as 8 / 16 / 32 bit wide.
Upgradeable footprint.
Package Suitable for Thermal Ladder Applications.
Single byte and Page Write operation.
DATA Polling and Toggle Bit for End of Write Detection.
Hardware and Software Data Protection.
May be screened in accordance with MIL-STD-883.
Block Diagram
Pin Definition
12
23
34
45
56
1
D8
2
WE2
13
D15
24
D24
35
VCC
46
D31
57
D9
CS2
14
D14
25
D25
36
CS4
47
D30
58
A0~A14
OE
WE4
WE3
WE2
WE1
3
D10
4
GND
15
D13
26
D26
37
WE4
48
D29
59
A13
5
D11
16
D12
27
A6
D27
49
D28
60
32K x 8
EEPROM
CS1
CS2
CS3
CS4
D0~7
D8~15
D16~23
D24~31
32K x 8
EEPROM
32K x 8
EEPROM
32K x 8
EEPROM
A14
6
A10
17
OE
28
NC
7
A11
18
NC
29
VIEW
FROM
ABOVE
38
A7
39
A3
50
A0
61
NC
40
A4
51
A1
62
NC
8
A12
19
WE1
30
A8
41
A5
52
A2
63
NC
9
VCC
20
D7
31
A9
42
WE3
53
D23
64
D0
10
CS1
21
D6
32
D16
43
CS3
54
D22
65
D1
11
NC
22
D5
33
D17
44
GND
55
D21
66
D2
D3
D4
D18
D19
D20
Pin Functions
A0-14
CS1-4
WE1-4
V
CC
Address Inputs
Chip Select
Write Enable
Power (+5V)
D0-31
OE
NC
GND
Data Inputs/Outputs
Output Enable
No Connect
Ground

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