PRELIMINARY DATA SHEET
MOS INTEGRATED CIRCUIT
μ
PD44646095, 44646185, 44646365, 44646097, 44646187, 44646367
72M-BIT DDR II+ SRAM SEPARATE I/O
2.0 & 2.5 Cycle Read Latency
2-WORD BURST OPERATION
Description
The
μ
PD44646095 and
μ
PD44646097 are 8,388,608-word by 9-bit, the
μ
PD44646185 and
μ
PD44646187 are
4,194,304-word by 18-bit and the
μ
PD44646365 and
μ
PD44646367 are 2,097,152-word by 36-bit synchronous double
data rate static RAMs fabricated with advanced CMOS technology using full CMOS six-transistor memory cell.
The
μ
PD44646xx5 is for 2.0 cycle and the
μ
PD44646xx7 is for 2.5 cycle read latency. The
μ
PD44646095,
μ
PD44646097,
μ
PD44646185,
μ
PD44646187,
μ
PD44646365 and
μ
PD44646367 integrate unique synchronous peripheral circuitry and a
burst counter. All input registers controlled by an input clock pair (K and K#) are latched on the positive edge of K and K#.
These products are suitable for application which require synchronous operation, high speed, low voltage, high density
and wide bit configuration.
These products are packaged in 165-pin PLASTIC BGA.
Features
•
Core (V
DD
) = 1.8 ± 0.1 V power supply
I/O (V
DD
Q) = 1.5 ± 0.1 V power supply
•
165-pin PLASTIC BGA (15x17)
•
HSTL interface
•
PLL circuitry for wide output data valid window and future frequency scaling
•
DDR read or write operation initiated each cycle
•
Pipelined double data rate operation
•
Separate data input/output bus
•
Two-tick burst for low DDR transaction size
•
Two input clocks (K and K#) for precise DDR timing at clock rising edges only
•
Two Echo clocks (CQ and CQ#)
•
Data Valid pin (QVLD) supported
•
Read latency : 2.0 & 2.5 clock cycles (Not selectable by user)
•
Internally self-timed write control
•
Clock-stop capability. Normal operation is restored in 2,048 cycles after clock is resumed.
•
User programmable impedance output (35 to 70
Ω)
•
Fast clock cycle time : 2.66 ns (375 MHz) for 2.0 cycle read latency,
2.5 ns (400 MHz) for 2.5 cycle read latency
•
Simple control logic for easy depth expansion
•
JTAG 1149.1 compatible test access port
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all products and/or types are available in every country. Please check with an NEC Electronics
sales representative for availability and additional information.
Document No. M18525EJ1V0DS00 (1st edition)
Date Published November 2006 NS CP(N)
Printed in Japan
2006
μ
PD44646095, 44646185, 44646365
,
44646097, 44646187, 44646367
Feature Differences between DDR II and DDR II+
Features
Frequency (DLL/PLL ON)
Organization
V
DD
V
DD
Q
Read Latency
Write Latency
Input Clocks (K, K#)
Output Clocks (C, C#)
Echo Clock Number (CQ, CQ#)
Package
QVLD
DDR II
120 MHz to 300 MHz
x8 / x9 / x18 / x36
1.8 ± 0.1 V
1.8 ± 0.1 V or 1.5 ± 0.1 V
1.5 clocks
1.0 clocks
Single Ended (K, K#)
Yes
1 Pair
165 (11x15) pin PLASTIC BGA
No
DDR II+
300 MHz to 400 MHz
x9 / x18 / x36
1.8 ± 0.1 V
1.5 ± 0.1 V
2.0 & 2.5 clocks
1.0 clocks
Single Ended (K, K#)
No
1 Pair
165 (11x15) pin PLASTIC BGA
Yes
4
3
1
2
Note
Notes 1.
DDR II+ read latency is not user selectable. Offered as two different devices.
2.
DDR II+ write latency is 1.0 cycle regardless of read latency.
3.
Echo Clocks are single-ended inputs.
4.
Edge aligned with Echo Clocks.
4
Preliminary Data Sheet M18525EJ1V0DS
μ
PD44646095, 44646185, 44646365
,
44646097, 44646187, 44646367
Pin Configurations
165-pin PLASTIC BGA (15x17)
(Top View)
[
μ
PD44646095], [
μ
PD44646097]
8M x 9-bit
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
CQ#
NC
NC
NC
NC
NC
NC
DLL#
NC
NC
NC
NC
NC
NC
TDO
2
A
NC
NC
D5
NC
NC
D6
V
REF
NC
NC
Q7
NC
D8
NC
TCK
3
A
NC
NC
NC
Q5
NC
Q6
V
DD
Q
NC
NC
D7
NC
NC
Q8
A
4
R, W#
A
V
SS
V
SS
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
SS
V
SS
A
A
5
NC
NC/288M
6
K#
K
A
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
A
QVLD
NC
7
NC/144M
8
LD#
A
V
SS
V
SS
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
SS
V
SS
A
A
9
A
NC
NC
NC
NC
NC
NC
V
DD
Q
NC
NC
NC
NC
NC
NC
A
10
A
NC
NC
NC
D3
NC
NC
V
REF
Q2
NC
NC
NC
NC
D0
TMS
11
CQ
Q4
D4
NC
Q3
NC
NC
ZQ
D2
NC
Q1
D1
NC
Q0
TDI
BW0#
A
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
A
A
A
A
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
A
A
A
A
D0 to D8
Q0 to Q8
LD#
R, W#
BW0#
K, K#
CQ, CQ#
ZQ
DLL#
QVLD
: Address inputs
: Data inputs
: Data outputs
: Synchronous load
: Read / Write input
: Byte Write data select
: Input clock
: Echo clock
: Output impedance matching
: DLL/PLL disable
: Q Valid output
TMS
TDI
TCK
TDO
V
REF
V
DD
V
DD
Q
V
SS
NC
NC/xxM
: IEEE 1149.1 Test input
: IEEE 1149.1 Test input
: IEEE 1149.1 Clock input
: IEEE 1149.1 Test output
: HSTL input reference input
: Power Supply
: Power Supply
: Ground
: No connection
: Expansion address for xxMb
Remarks 1.
×××#
indicates active LOW signal.
2.
Refer to
Package Drawing
for the index mark.
3.
7A and 5B are expansion addresses:7A for 144Mb and 5B for 288Mb.
Preliminary Data Sheet M18525EJ1V0DS
5
DSP and ARM Processors
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