BUK9640-100A
13 March 2014
D2
PA
K
N-channel TrenchMOS logic level FET
Product data sheet
1. General description
Logic level N-channel enhancement mode Field-Effect Transistor (FET) in a plastic
package using TrenchMOS technology. This product has been designed and qualified to
the appropriate AEC standard for use in automotive critical applications.
2. Features and benefits
•
•
•
•
Low conduction losses due to low on-state resistance
Q101 compliant
Suitable for logic level gate drive sources
Suitable for thermally demanding environments due to 175 °C rating
3. Applications
•
•
•
12 V, 24 V and 42 V loads
Automotive and general purpose power switching
Motors, lamps and solenoids
4. Quick reference data
Table 1.
Symbol
V
DS
I
D
P
tot
R
DSon
Quick reference data
Parameter
drain-source voltage
drain current
total power dissipation
Conditions
T
j
≥ 25 °C; T
j
≤ 175 °C
V
GS
= 5 V; T
mb
= 25 °C;
Fig. 2; Fig. 3
T
mb
= 25 °C;
Fig. 1
V
GS
= 4.5 V; I
D
= 25 A; T
j
= 25 °C
V
GS
= 10 V; I
D
= 25 A; T
j
= 25 °C
V
GS
= 5 V; I
D
= 25 A; T
j
= 25 °C;
Fig. 11; Fig. 12
Dynamic characteristics
Q
GD
gate-drain charge
V
GS
= 5 V; I
D
= 25 A; V
DS
= 80 V;
T
j
= 25 °C;
Fig. 13
-
20
-
nC
Min
-
-
-
Typ
-
-
-
Max
100
39
158
Unit
V
A
W
Static characteristics
drain-source on-state
resistance
-
-
-
-
29
34
43
39
40
mΩ
mΩ
mΩ
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NXP Semiconductors
BUK9640-100A
N-channel TrenchMOS logic level FET
Symbol
E
DS(AL)S
Parameter
non-repetitive drain-
source avalanche
energy
Conditions
I
D
= 39 A; V
sup
≤ 100 V; R
GS
= 50 Ω;
V
GS
= 5 V; T
j(init)
= 25 °C; unclamped
Min
-
Typ
-
Max
182
Unit
mJ
Avalanche ruggedness
5. Pinning information
Table 2.
Pin
1
2
3
mb
Pinning information
Symbol Description
G
D
S
D
gate
drain
[1]
source
mounting base; connected to
drain
2
1
3
G
mbb076
Simplified outline
mb
Graphic symbol
D
S
D2PAK (SOT404)
[1]
It is not possible to make a connection to pin 2.
6. Ordering information
Table 3.
Ordering information
Package
Name
BUK9640-100A
D2PAK
Description
Version
plastic single-ended surface-mounted package (D2PAK); 3 leads SOT404
(one lead cropped)
Type number
7. Marking
Table 4.
Marking codes
Marking code
BUK9640-100A
Type number
BUK9640-100A
8. Limiting values
Table 5.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
V
DS
V
DGR
V
GS
BUK9640-100A
Parameter
drain-source voltage
drain-gate voltage
gate-source voltage
Conditions
T
j
≥ 25 °C; T
j
≤ 175 °C
R
GS
= 20 kΩ
Min
-
-
-15
Max
100
100
15
Unit
V
V
V
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved
Product data sheet
13 March 2014
2 / 13
NXP Semiconductors
BUK9640-100A
N-channel TrenchMOS logic level FET
Symbol
P
tot
I
D
Parameter
total power dissipation
drain current
Conditions
T
mb
= 25 °C;
Fig. 1
T
mb
= 25 °C; V
GS
= 5 V;
Fig. 2; Fig. 3
T
mb
= 100 °C; V
GS
= 5 V;
Fig. 2
Min
-
-
-
-
-55
-55
Max
158
39
28
159
175
175
Unit
W
A
A
A
°C
°C
I
DM
T
stg
T
j
I
S
I
SM
E
DS(AL)S
peak drain current
storage temperature
junction temperature
T
mb
= 25 °C; pulsed; t
p
≤ 10 µs;
Fig. 3
Source-drain diode
source current
peak source current
T
mb
= 25 °C
pulsed; t
p
≤ 10 µs; T
mb
= 25 °C
I
D
= 39 A; V
sup
≤ 100 V; R
GS
= 50 Ω;
V
GS
= 5 V; T
j(init)
= 25 °C; unclamped
03na19
-
-
39
159
A
A
Avalanche ruggedness
non-repetitive drain-source
avalanche energy
-
182
mJ
120
P
der
(%)
80
40
I
D
(A)
30
03nh74
20
40
10
0
0
50
100
150
T
mb
(°C)
200
0
25
50
75
100
125
150
175
200
T
mb
(°C)
Fig. 1.
Normalized total power dissipation as a
function of mounting base temperature
Fig. 2.
Normalized continuous drain current as a
function of mounting base temperature
BUK9640-100A
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved
Product data sheet
13 March 2014
3 / 13
NXP Semiconductors
BUK9640-100A
N-channel TrenchMOS logic level FET
10
3
I
D
(A)
10
2
R
DSon
= V
DS
/ I
D
t
p
= 10 µs
03nh72
100 µs
10
DC
1 ms
10 ms
100 ms
1
1
10
10
2
10
3
V
DS
(V)
Fig. 3.
Safe operating area; continuous and peak drain currents as a function of drain-source voltage
9. Thermal characteristics
Table 6.
Symbol
R
th(j-mb)
Thermal characteristics
Parameter
thermal resistance
from junction to
mounting base
thermal resistance
from junction to
ambient
1
Z
th(j-mb)
(K/W)
δ = 0.5
0.2
10
- 1
0.1
0.05
0.02
10
- 2
P
Single Shot
δ=
t
p
T
Conditions
Fig. 4
Min
-
Typ
-
Max
0.95
Unit
K/W
R
th(j-a)
mounted on a printed-circuit board;
minimum footprint
-
50
-
K/W
03nh73
t
p
10
- 3
10
- 6
10
- 5
10
- 4
10
- 3
10
- 2
10
- 1
t
T
t
p
(s)
1
Fig. 4.
Transient thermal impedance from junction to mounting base as a function of pulse duration
BUK9640-100A
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved
Product data sheet
13 March 2014
4 / 13
NXP Semiconductors
BUK9640-100A
N-channel TrenchMOS logic level FET
10. Characteristics
Table 7.
Symbol
V
(BR)DSS
Characteristics
Parameter
drain-source
breakdown voltage
gate-source threshold
voltage
Conditions
I
D
= 0.25 mA; V
GS
= 0 V; T
j
= 25 °C
I
D
= 0.25 mA; V
GS
= 0 V; T
j
= -55 °C
I
D
= 1 mA; V
DS
= V
GS
; T
j
= 25 °C;
Fig. 10
I
D
= 1 mA; V
DS
= V
GS
; T
j
= 175 °C;
Fig. 10
I
D
= 1 mA; V
DS
= V
GS
; T
j
= -55 °C;
Fig. 10
I
DSS
drain leakage current
V
DS
= 100 V; V
GS
= 0 V; T
j
= 175 °C
V
DS
= 100 V; V
GS
= 0 V; T
j
= 25 °C
I
GSS
gate leakage current
V
GS
= 10 V; V
DS
= 0 V; T
j
= 25 °C
V
GS
= -10 V; V
DS
= 0 V; T
j
= 25 °C
R
DSon
drain-source on-state
resistance
V
GS
= 4.5 V; I
D
= 25 A; T
j
= 25 °C
V
GS
= 5 V; I
D
= 25 A; T
j
= 175 °C;
Fig. 11; Fig. 12
V
GS
= 10 V; I
D
= 25 A; T
j
= 25 °C
V
GS
= 5 V; I
D
= 25 A; T
j
= 25 °C;
Fig. 11; Fig. 12
Dynamic characteristics
Q
G(tot)
Q
GS
Q
GD
C
iss
C
oss
C
rss
t
d(on)
t
r
t
d(off)
t
f
L
D
total gate charge
gate-source charge
gate-drain charge
input capacitance
output capacitance
reverse transfer
capacitance
turn-on delay time
rise time
turn-off delay time
fall time
internal drain
inductance
from upper edge of drain mounting
base to centre of die; T
j
= 25 °C
V
DS
= 30 V; R
L
= 1.2 Ω; V
GS
= 5 V;
R
G(ext)
= 10 Ω; T
j
= 25 °C
V
GS
= 0 V; V
DS
= 25 V; f = 1 MHz;
T
j
= 25 °C;
Fig. 14
I
D
= 25 A; V
DS
= 80 V; V
GS
= 5 V;
T
j
= 25 °C;
Fig. 13
-
-
-
-
-
-
-
-
-
-
-
48
5.4
20
2304
222
151
20
135
125
90
2.5
-
-
-
3072
266
207
-
-
-
-
-
nC
nC
nC
pF
pF
pF
ns
ns
ns
ns
nH
-
-
29
34
39
40
mΩ
mΩ
-
-
-
-
-
-
-
0.05
2
2
-
-
500
10
100
100
43
100
µA
µA
nA
nA
mΩ
mΩ
-
-
2.3
V
0.5
-
-
V
Min
100
89
1
Typ
-
-
1.5
Max
-
-
2
Unit
V
V
V
Static characteristics
V
GS(th)
BUK9640-100A
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved
Product data sheet
13 March 2014
5 / 13
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