Description
SK hynix VLP (Very Low Profile) registered DDR3 SDRAM DIMMs (Registered Double Data Rate Synchro-
nous DRAM Dual In-Line Memory Modules) are low power, high-speed operation memory modules that use
DDR3 SDRAM devices. These Registered SDRAM DIMMs are intended for use as main memory when
installed in systems such as servers and workstations.
Features
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Power Supply: VDD=1.5V (1.425V to 1.575V)
VDDQ = 1.5V (1.425V to 1.575V)
VDDSPD=3.0V to 3.6V
8 internal banks
Data transfer rates: PC3-14900, PC3-12800, PC3-10600
Bi-Directional Differential Data Strobe
8 bit pre-fetch
Burst Length (BL) switch on-the-fly BL8 or BC4(Burst Chop)
Supports ECC error correction and detection
On-Die Termination (ODT)
Temperature sensor with integrated SPD
This product is in compliance with the RoHS directive.
Ordering Information
Part Number
HMT325V7EFR8C-H9/PB/RD
HMT351V7EFR4C-H9/PB/RD
HMT351V7EFR8C-H9/PB/RD
Density
2GB
4GB
4GB
Organization
256Mx72
512Mx72
512Mx72
Component Composition
256Mx8(H5TQ2G83EFR)*9
512Mx4(H5TQ2G43EFR)*18
256Mx8(H5TQ2G83EFR)*18
# of
ranks
1
1
2
FDHS
X
X
X
* In order to uninstall FDHS, please contact sales administrator
Rev. 0.1 / Dec. 2012
3
Pin Descriptions
Pin Name
CK0
CK0
CK1
CK1
CKE[1:0]
RAS
Description
Clock Input, positive line
Clock Input, negative line
Clock Input, positive line
Clock Input, negative line
Clock Enables
Row Address Strobe
Num
ber
1
1
1
1
2
1
Pin Name
ODT[1:0]
DQ[63:0]
CB[7:0]
DQS[8:0]
DQS[8:0]
DM[8:0]/
DQS[17:9],
TDQS[17:9]
DQS[17:9],
TDQS[17:9]
EVENT
TEST
RESET
V
DD
V
SS
V
REFDQ
V
REFCA
V
TT
V
DDSPD
Description
On Die Termination Inputs
Data Input/Output
Data check bits Input/Output
Data strobes
Data strobes, negative line
Data Masks / Data strobes,
Termination data strobes
Data strobes, negative line,
Termination data strobes
Reserved for optional hardware
temperature sensing
Memory bus test tool (Not Con-
nected and Not Usable on DIMMs)
Register and SDRAM control pin
Power Supply
Ground
Reference Voltage for DQ
Reference Voltage for CA
Termination Voltage
SPD Power
Num
ber
2
64
8
9
9
9
CAS
WE
S[3:0]
A[9:0],A11,
A[15:13]
A10/AP
A12/BC
BA[2:0]
SCL
SDA
SA[2:0]
Par_In
Err_Out
Column Address Strobe
Write Enable
Chip Selects
Address Inputs
Address Input/Autoprecharge
Address Input/Burst chop
SDRAM Bank Addresses
Serial Presence Detect (SPD)
Clock Input
SPD Data Input/Output
SPD Address Inputs
Parity bit for the Address and
Control bus
Parity error found on the
Address and Control bus
1
1
4
14
1
1
3
1
1
3
1
1
9
1
1
1
22
59
1
1
4
1
Rev. 0.1 / Dec. 2012
5
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