MC9S12DJ512CPV datasheet, PDF - EEWORLD Datasheet

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MC9S12DJ512CPV: Description16-BIT, FLASH, 25MHz, MICROCONTROLLER, PQFP112, LQFP-112; CategoryThe embedded processor and controller Microcontrollers and processors; File Size5MB，124 Pages; ManufacturerNXP; Websitehttps://www.nxp.com

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MC9S12DJ512CPV Overview

16-BIT, FLASH, 25MHz, MICROCONTROLLER, PQFP112, LQFP-112

MC9S12DJ512CPV Parametric

Parameter Name	Attribute value
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Maker	NXP
Parts packaging code	QFP
package instruction	LQFP-112
Contacts	112
Reach Compliance Code	unknown
ECCN code	EAR99
Has ADC	YES
Other features	ALSO REQUIRES 5V SUPPLY
Address bus width	20
bit size	16
CPU series	CPU12
maximum clock frequency	50 MHz
DAC channel	NO
DMA channel	NO
External data bus width	16
JESD-30 code	S-PQFP-G112
JESD-609 code	e0
length	20 mm
Humidity sensitivity level	3
Number of I/O lines	91
Number of terminals	112
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
PWM channel	YES
Package body material	PLASTIC/EPOXY
encapsulated code	LQFP
Encapsulate equivalent code	QFP112,.87SQ
Package shape	SQUARE
Package form	FLATPACK, LOW PROFILE
Peak Reflow Temperature (Celsius)	220
power supply	2.5,5 V
Certification status	Not Qualified
RAM (bytes)	14336
rom(word)	524288
ROM programmability	FLASH
Maximum seat height	1.6 mm
speed	25 MHz
Maximum supply voltage	2.75 V
Minimum supply voltage	2.35 V
Nominal supply voltage	2.5 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	GULL WING
Terminal pitch	0.65 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	30
width	20 mm
uPs/uCs/peripheral integrated circuit type	MICROCONTROLLER

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Freescale Semiconductor

DOCUMENT NUMBER

9S12DP512DGV1/D

MC9S12DP512

Device Guide

V01.25

Covers also

MC9S12DT512, MC9S12DJ512,

MC9S12A512

Original Release Date: 27 Nov 2001

Revised: 05 Jul 2005

Freescale Semiconductor, Inc.

MC9S12DP512 Device Guide V01.25

Table of Contents

Section 1 Introduction

1.1

1.2

1.3

1.4

1.5

1.5.1

1.6

1.7

Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22

Device Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

Detailed Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

Part ID Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49

Memory Size Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49

Section 2 Signal Description

2.1

Device Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52

2.2

Signal Properties Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53

2.3

Detailed Signal Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55

2.3.1

EXTAL, XTAL — Oscillator Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55

2.3.2

RESET — External Reset Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55

2.3.3

TEST — Test Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55

2.3.4

VREGEN — Voltage Regulator Enable Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55

2.3.5

XFC — PLL Loop Filter Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56

2.3.6

BKGD / TAGHI / MODC — Background Debug, Tag High, and Mode Pin . . . . . . . .56

2.3.7

PAD15 / AN15 / ETRIG1 — Port AD Input Pin of ATD1 . . . . . . . . . . . . . . . . . . . . . .56

2.3.8

PAD[14:08] / AN[14:08] — Port AD Input Pins of ATD1 . . . . . . . . . . . . . . . . . . . . . .56

2.3.9

PAD7 / AN07 / ETRIG0 — Port AD Input Pin of ATD0 . . . . . . . . . . . . . . . . . . . . . . .56

2.3.10 PAD[06:00] / AN[06:00] — Port AD Input Pins of ATD0 . . . . . . . . . . . . . . . . . . . . . .56

2.3.11 PA[7:0] / ADDR[15:8] / DATA[15:8] — Port A I/O Pins . . . . . . . . . . . . . . . . . . . . . . .57

2.3.12 PB[7:0] / ADDR[7:0] / DATA[7:0] — Port B I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . .57

2.3.13 PE7 / NOACC / XCLKS — Port E I/O Pin 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57

2.3.14 PE6 / MODB / IPIPE1 — Port E I/O Pin 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58

2.3.15 PE5 / MODA / IPIPE0 — Port E I/O Pin 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58

2.3.16 PE4 / ECLK — Port E I/O Pin 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58

2.3.17 PE3 / LSTRB / TAGLO — Port E I/O Pin 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59

2.3.18 PE2 / R/W — Port E I/O Pin 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59

2.3.19 PE1 / IRQ — Port E Input Pin 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59

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