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HY51V65160ALTC-50

Description
Fast Page DRAM, 4MX16, 50ns, CMOS, PDSO50, 0.400 INCH, PLASTIC, TSOP2-50
Categorystorage    storage   
File Size94KB,9 Pages
ManufacturerSK Hynix
Websitehttp://www.hynix.com/eng/
Download Datasheet Parametric View All

HY51V65160ALTC-50 Overview

Fast Page DRAM, 4MX16, 50ns, CMOS, PDSO50, 0.400 INCH, PLASTIC, TSOP2-50

HY51V65160ALTC-50 Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
MakerSK Hynix
Parts packaging codeTSOP2
package instructionTSOP2, TSOP50,.46,32
Contacts50
Reach Compliance Codecompliant
ECCN codeEAR99
access modeFAST PAGE
Maximum access time50 ns
Other featuresRAS ONLY/CAS BEFORE RAS/HIDDEN/SELF REFRESH
I/O typeCOMMON
JESD-30 codeR-PDSO-G50
JESD-609 codee0
length20.95 mm
memory density67108864 bit
Memory IC TypeFAST PAGE DRAM
memory width16
Number of functions1
Number of ports1
Number of terminals50
word count4194304 words
character code4000000
Operating modeASYNCHRONOUS
Maximum operating temperature70 °C
Minimum operating temperature
organize4MX16
Output characteristics3-STATE
Package body materialPLASTIC/EPOXY
encapsulated codeTSOP2
Encapsulate equivalent codeTSOP50,.46,32
Package shapeRECTANGULAR
Package formSMALL OUTLINE, THIN PROFILE
power supply3.3 V
Certification statusNot Qualified
refresh cycle4096
Maximum seat height1.2 mm
self refreshNO
Maximum standby current0.0003 A
Maximum slew rate0.14 mA
Maximum supply voltage (Vsup)3.6 V
Minimum supply voltage (Vsup)3 V
Nominal supply voltage (Vsup)3.3 V
surface mountYES
technologyCMOS
Temperature levelCOMMERCIAL
Terminal surfaceTin/Lead (Sn/Pb)
Terminal formGULL WING
Terminal pitch0.8 mm
Terminal locationDUAL
width10.16 mm
HY51V64160A,HY51V65160A
4Mx16, Fast Page mode
2nd Generation
DESCRIPTION
This family is a 64M bit dynamic RAM organized 4,194,304 x 16-bit configuration with Fast Page mode CMOS DRAMs.
Fast Page mode offers high speed of random access memory within the same row. The circuit and process design allow
this device to achieve high performance and low power dissipation. Optional features are access time(60 or 70ns) and
refresh cycle(8K ref. or 4K ref.) and power consumption (Normal or Low power with self refresh). Hyundai’s advanced
circuit design and process technology allow this device to achieve high bandwidth, low power consumption and high
reliability.
FEATURES
Ÿ
Fast page mode operation
Ÿ
Read-modify-write capability
Ÿ
Multi-bit parallel test capability
Ÿ
LVTTL(3.3V) compatible inputs and outputs
Ÿ
/CAS-before-/RAS, /RAS-only, Hidden and
Self refresh capability
Ÿ
Max. Active power dissipation
Speed
50
60
Ÿ
Refresh cycles
Part number
HY51V64160A
1)
HY51V65160A
2)
Refresh
8K
64ms
4K
128ms
Normal
L-part
8K refresh
396mW
324mW
4K refresh
504mW
432mW
Ÿ
JEDEC standard pinout
50-pin plastic TSOP-II (400mil)
Ÿ
Single power supply of 3.3
±
0.3V
Ÿ
Early write or output enable controlled write
Ÿ
Fast access time and cycle time
Speed
50
60
tRAC
50ns
60ns
tCAC
13ns
15ns
tPC
35ns
40ns
1) Normal read / write, /RAS only refresh : 8K cycles / 64ms
/CAS-before-/RAS, Hidden refresh
: 4K cycles / 64ms
2) Normal read / write, /RAS only refresh : 4K cycles / 64ms
/CAS-before-/RAS, Hidden refresh
: 4K cycles / 64ms
ORDERING INFORMATION
Part Name
HY51V64160ATC
HY51V64160ALTC
HY51V64160ASLTC
HY51V65160ATC
HY51V65160ALTC
HY51V65160ASLTC
*SL : Self refresh with low power.
Refresh
8K
8K
8K
4K
4K
4K
Power
Package
50Pin TSOP-II
L-part
*SL-part
50Pin TSOP-II
50Pin TSOP-II
50Pin TSOP-II
L-part
*SL-part
50Pin TSOP-II
50Pin TSOP-II
This document is a general product description and is subject to change without notice. Hyundai electronics does not assume any responsibility for use of
circuits described. No patent licences are implied
Hyundai Semiconductor
Rev.12/Sep.98
1

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