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www.fairchildsemi.com
FAN5660
Monolithic Inductorless CMOS DC/DC Converter
Features
•
•
•
•
•
•
•
Inverts, Doubles or Splits Input Supply Voltage
90% Typ Conversion Efficiency at 100mA load current
0.5V Typ Loss at 100mA Load
Low 160µA Operating Current
5.
0Ω
Typ Output Resistance for C1 = C2 = 100µF
Selectable Oscillator Frequency: 5kHz/50kHz
8-pin SOIC package.
General Description
The FAN5660 is a monolithic charge-pump which can
invert, double or split a +1.5V to +5.5V input voltage.
Using only two identical low-cost capacitors, the charge
pump replaces switching regulators, thus eliminating
inductors and their associated cost, size, and EMI. The
device has a greater than 90% efficiency over most of its load
current range and a typical operating current of only 160µA.
The FAN5660 is ideal for both battery-powered and board-
level voltage conversion applications.
In order to enable the user optimize capacitor size and
quiescent current, the FAN5660 is offered with a frequency
control (FC) pin which selects either 5kHz or 50kHz
operation.
The Oscillator frequency can also be driven with an external
clock. The FAN5660 is available in 8-pin small-outline
packages.
Applications
•
•
•
•
•
Laptop Computers
Medical Instruments
Interface Power Supplies
Hand-Held Instruments
Operational-Amplifier Power Supplies
Simplified Block Diagram
CAP+
CAP–
VSS
V+
VSH
CONTROL
LV
SYNC
OSCILLATOR
FC
REV. 1.0.2 3/28/02
FAN5660
Pin Configuration
FC 1
CAP+ 2
FAN5660
VSS 3
CAP-
4
SOIC
6
5
LV
VSH
8
7
V+
SYNC
Typical Applications
V
IN
FC
CAP+
+
C1
VSS
CAP-
V+
SYNC
FC
CAP+
V+
+
SYNC
C2
V
OUT
= 2V
IN
LV
V
OUT
= –V
IN
VSH
R
L
+
C2
+
C1
+V
IN
VSS
CAP-
LV
VSH
C1 = C2 = 1 to 470µF
C1 = C2 = 1 to 470µF
Figure 1. Inverter, Test Circuit
Figure 2. Doubler
FC
CAP+
+
V
OUT
= –V
IN
/2
C1
VSS
CAP-
C2
FAN5660
V+
SYNC
V
IN
LV
+
VSH
C1 = C2 = 1 to 470µF
Figure 3. Splitter
2
REV. 1.0.2 3/28/02
FAN5660
Pin Definition
Pin
Number
1
Pin
Name
FC
Pin Function Description
Inverter
Splitter
Doubler
Same as Inverter
Frequency Control for Internal
Same as Inverter
Oscillator, FC open, f
OSC
= 5kHz
typ; FC = V+, f
OSC
= 50kHz typ.
FC has no effect when SYNC pin is
driven externally
Charge-Pump Capacitor, Positive
Terminal
Power-Supply Ground Input
Charge-Pump Capacitor,
Negative Terminal
Output, Negative Voltage
Low-Voltage Operation Input.
Tie LV to VSS when input voltage is
less than 2V.
Above 2V, LV must be left open.
Oscillator Control Input.
An external Oscillator may be
connected to overdrive SYNC via a
2 to 5 nF capacitor.
SYNC shall not be connected to a
low impedance DC voltage
8
V+
Power-Supply Positive Voltage
Input
Positive Voltage Input
Positive Voltage Output
Same as Inverter
Power-Supply
Positive Voltage Output
Same as Inverter
Power-Supply
Ground Input
LV must be left open for all
input voltages
2
3
4
5
6
CAP+
VSS
CAP-
VSH
LV
Same as Inverter
Power-Supply
Positive Voltage Input
Same as Inverter
Power-Supply
Ground Input
LV must be left open for
all input voltages
7
SYNC
Same as inverter, however, Same as inverter,
do not use SYNC in
however, do not use
voltage-splitting mode.
SYNC in voltage-
doubling mode.
REV. 1.0.2 3/28/02
3
FAN5660
Absolute Maximum Ratings
Absolute maximum ratings are the values beyond which the device may be damaged or have its useful life
impaired. Functional operation under these conditions is not implied.
Parameter
Supply Voltage: V+ to VSS
VSH Voltage to VSS
Voltage on all other pin to VSS
VSH and V+ Continuous Output Current (
Note 1
)
Junction Temperature
Storage Temperature
Lead Soldering Temperature, 10 seconds
Electrostatic Discharge Protection (
Note 2
)
Power Dissipation (P
D
) at 85C
4
300
-40
Min.
-0.3
-6
-0.3
Max.
6
0.3
(V+) + 0.3
120
125
150
300
Units
V
V
V
mA
°C
°C
°C
kV
mW
Notes
1. VSH must not be shorted to VSS or V+, even instantaeously, or device damage may result.
2. Using Mil Std. 883E, method 3015.7(Human Body Model), 400V when using JEDEC method A115-A (Machine Model).
Recommended Operating Conditions
Parameter
Supply Voltage V+ to VSS or VSS to VSH
External SYNC signal
Ambient Operating Temperature
Conditions
LV open
LV = VSS
Connected via
C =2 to 5 nF
T
A
-40
Min.
2
1.5
2
85
Typ.
Max.
5.5
2
V peak
to peak
°
C
Units
V
Electrical Specifications
V+ = 5V, R
L
=
∞
, and T
A
= +25°C using circuit in Figure 1 with C1 = C2 = 100µF, FC and LV open, unless otherwise
specified (Note 3)
Parameter
Quiescent Current
Output Current
Output Resistance
Oscillator Frequency
Power Efficiency
Symbol
I
IN
I
VSH
R
VSH
f
OSC
η
FC open
FC to V+
VSH more negative than -4V
100mA load current
FC open
FC to V+
RL=1k
Ω
RL=0.5k
Ω
100mA load current
Voltage Conversion Efficiency
η
V
99
2.5
30
96
92
100
5
5
50
98
96
90
99.96
%
8
10
90
%
Conditions
Min.
Typ.
0.16
1
Max.
0.5
2
mA
Ω
kHz
Units
mA
Note
3 . In the test circuit, capacitors C1 and C2 are 0.2
Ω
maximum ESR capacitors. Capacitors with higher ESR will increase output
resistance, reduce output voltage and efficiency.
4
REV. 1.0.2 3/28/02
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