SN74LS257B, SN74LS258B
Quad 2-Input Multiplexer
with 3-State Outputs
The LSTTL/MSI SN74LS257B and the SN74LS258B are Quad
2-Input Multiplexers with 3-state outputs. Four bits of data from two
sources can be selected using a Common Data Select input. The four
outputs present the selected data in true (non-inverted) form. The
outputs may be switched to a high impedance state with a HIGH on the
common Output Enable (EO) Input, allowing the outputs to interface
directly with bus oriented systems. It is fabricated with the Schottky
barrier diode process for high speed and is completely compatible with
all ON Semiconductor TTL families.
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LOW
POWER
SCHOTTKY
PLASTIC
N SUFFIX
CASE 648
1
•
•
•
•
•
•
Schottky Process For High Speed
Multiplexer Expansion By Tying Outputs Together
Non-Inverting 3-State Outputs
Input Clamp Diodes Limit High Speed Termination Effects
Special Circuitry Ensures Glitch Free Multiplexing
ESD > 3500 Volts
16
GUARANTEED OPERATING RANGES
16
Symbol
VCC
TA
IOH
IOL
Parameter
Supply Voltage
Operating Ambient
Temperature Range
Output Current – High
Output Current – Low
Min
4.75
0
Typ
5.0
25
Max
5.25
70
–2.6
24
Unit
V
°C
mA
mA
SOIC
D SUFFIX
CASE 751B
1
16
1
SOEIAJ
M SUFFIX
CASE 966
ORDERING INFORMATION
Device
SN74LS257BN
SN74LS257BD
SN74LS257BDR2
SN74LS257BM
SN74LS257BMEL
SN74LS258BN
SN74LS258BD
SN74LS258BDR2
SN74LS258BM
SN74LS258BMEL
Package
16 Pin DIP
SOIC–16
SOIC–16
SOEIAJ–16
SOEIAJ–16
16 Pin DIP
SOIC–16
SOIC–16
SOEIAJ–16
SOEIAJ–16
Shipping
2000 Units/Box
38 Units/Rail
2500/Tape & Reel
See Note 1
See Note 1
2000 Units/Box
38 Units/Rail
2500/Tape & Reel
See Note 1
See Note 1
1. For ordering information on the EIAJ version of
the SOIC package, please contact your local
ON Semiconductor representative.
©
Semiconductor Components Industries, LLC, 2001
1
October, 2001 – Rev. 7
Publication Order Number:
SN74LS257B/D
SN74LS257B, SN74LS258B
CONNECTION DIAGRAM DIP
(TOP VIEW)
VCC
16
E0
15
I0c
14
I1c
13
Zc
12
I0d
11
I1d
10
Zd
9
SN74LS257B
VCC = PIN 16
GND = PIN 8
1
S
VCC
16
2
I0a
E0
15
3
I1a
I0c
14
4
Za
I1c
13
5
I0b
Zc
12
6
I1b
I0d
11
7
Zb
I1d
10
8
GND
Zd
9
NOTE:
The Flatpak version has the same
pinouts (Connection Diagram) as
the Dual In Line Package.
SN74LS258B
1
S
2
I0a
3
I1a
4
Za
5
I0b
6
I1b
7
Zb
8
GND
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2
SN74LS257B, SN74LS258B
LOGIC DIAGRAMS
SN74LS257B
E0
15
I0a
2
I1a
3
I0b
5
I1b
6
I0c
14
I1c
13
I0d
11
I1d
10
S
1
4
7
12
9
Za
Zb
Zc
Zd
SN74LS258B
E0
15
I0a
2
I1a
3
I0b
5
I1b
6
I0c
14
I1c
13
I0d
11
I1d
10
S
1
V
CC
= PIN 16
GND = PIN 8
4
7
12
9
= PIN NUMBERS
Za
Zb
Zc
Zd
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3
SN74LS257B, SN74LS258B
FUNCTIONAL DESCRIPTION
The LS257B and LS258B are Quad 2-Input Multiplexers
with 3-state outputs. They select four bits of data from two
sources each under control of a Common Data Select Input.
When the Select Input is LOW, the I0 inputs are selected and
when Select is HIGH, the I1 inputs are selected. The data on
the selected inputs appears at the outputs in true
(non-inverted) form for the LS257B and in the inverted form
for the LS258B.
The LS257B and LS258B are the logic implementation of
a 4-pole, 2-position switch where the position of the switch
is determined by the logic levels supplied to the Select Input.
The logic equations for the outputs are shown below:
LS257B
Za = E0
•
(I1a
•
S + I0a
•
S) Zb = E0
•
(I1b
•
S +
Zc = E0
•
(I1c
•
S + I0c
•
S) Zd = E0
•
(I1d
•
S +
I0b
•
S)
I0d
•
S)
When the Output Enable Input (E0) is HIGH, the outputs
are forced to a high impedance “off” state. If the outputs are
tied together, all but one device must be in the high
impedance state to avoid high currents that would exceed the
maximum ratings. Designers should ensure that Output
Enable signals to 3-state devices whose outputs are tied
together are designed so there is no overlap.
LS258B
Za = E0
•
(I1a
•
S + I0a
•
S) Zb = E0
•
(I1b
•
S +
Zc = E0
•
(I1c
•
S + I0c
•
S) Zd = E0
•
(I1d
•
S +
I0b
•
S)
I0d
•
S)
TRUTH TABLE
OUTPUT
ENABLE
EO
H
L
L
L
L
SELECT
INPUT
S
X
H
H
L
L
DATA
INPUTS
I0
X
X
X
L
H
I1
X
L
H
X
X
OUTPUTS
LS257B
Z
(Z)
L
H
L
H
OUTPUTS
LS258B
Z
(Z)
H
L
H
L
H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
(Z) = High Impedance (off)
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4
SN74LS257B, SN74LS258B
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE
(unless otherwise specified)
Limits
Symbol
VIH
VIL
VIK
VOH
Parameter
Input HIGH Voltage
Input LOW Voltage
Input Clamp Diode Voltage
Output HIGH Voltage
2.4
–0.65
3.1
0.25
VOL
IOZH
IOZL
Output LOW Voltage
0.35
Output Off Current — HIGH
Output Off Current — LOW
Input HIGH Current
Other Inputs
S Inputs
Other Inputs
S Inputs
IIL
IOS
Input LOW Current
All Inputs
Short Circuit Current (Note 2)
Power Supply Current
Total, Output HIGH
ICC
Total, Output LOW
Total, Output 3-State
LS257B
LS258B
LS257B
LS258B
LS257B
LS258B
10
9.0
16
14
19
16
mA
VCC = MAX
–30
0.5
20
–20
20
40
0.1
0.2
–0.4
–130
V
µA
µA
µA
0.4
Min
2.0
0.8
–1.5
Typ
Max
Unit
V
V
V
V
V
Test Conditions
Guaranteed Input HIGH Voltage for
All Inputs
Guaranteed Input LOW Voltage for
All Inputs
VCC = MIN, IIN = –18 mA
VCC = MIN, IOH = MAX, VIN = VIH
or VIL per Truth Table
IOL = 12 mA
IOL = 24 mA
VCC = VCC MIN,
VIN = VIL or VIH
per Truth Table
VCC = MAX, VOUT = 2.7 V
VCC = MAX, VOUT = 0.4 V
VCC = MAX, VIN = 2.7 V
IIH
mA
mA
mA
VCC = MAX, VIN = 7.0 V
VCC = MAX, VIN = 0.4 V
VCC = MAX
mA
mA
2. Not more than one output should be shorted at a time, nor for more than 1 second.
AC CHARACTERISTICS
(TA = 25°C, VCC = 5.0 V) See SN74LS251 for Waveforms
Limits
Symbol
tPLH
tPHL
tPLH
tPHL
tPZH
tPZL
tPLZ
tPHZ
Parameter
Propagation Delay, Data to Output
Propagation Delay, Select to Output
Output Enable Time to HIGH Level
Output Enable Time to LOW Level
Output Disable Time to LOW Level
Output Disable Time from HIGH Level
Min
Typ
10
12
14
14
20
20
16
18
Max
13
15
21
21
25
25
25
25
Unit
ns
ns
ns
ns
ns
ns
Test Conditions
Figures 1 & 2
CL = 45 pF
Figures 1 & 2
Figures 4 & 5
Figures 3 & 5
Figures 3 & 5
Figures 4 & 5
CL = 45 pF
F
RL = 667
Ω
CL = 5.0 pF
F
RL = 667
Ω
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5
PCB Design
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