K9K1208Q0C
K9K1208D0C
K9K1208U0C
K9K1216Q0C
K9K1216D0C
K9K1216U0C
FLASH MEMORY
Document Title
64M x 8 Bit , 32M x 16 Bit NAND Flash Memory
Revision History
Revision No. History
0.0
1.0
Initial issue.
1.Pin assignment of TBGA dummy ball is changed.
(before) DNU --> (after) N.C
2. Add the Rp vs tr ,tf & Rp vs ibusy graph for 1.8V device (Page 34)
3. Add the data protection Vcc guidence for 1.8V device - below about
1.1V. (Page 35)
4. Add the specification of Block Lock scheme.(Page 29~32)
5. Pin assignment of TBGA A3 ball is changed.
(before) N.C --> (after) Vss
2.0
1. The Maximum operating current is changed.
Read : Icc1 20mA-->30mA
Program : Icc2 20mA-->40mA
Erase : Icc3 20mA-->40mA
The min. Vcc value 1.8V devices is changed.
K9K12XXQ0C : Vcc 1.65V~1.95V --> 1.70V~1.95V
Pb-free Package is added.
K9K1208U0C-HCB0,HIB0
K9K12XXQ0C-HCB0,HIB0
K9K1216U0C-HCB0,HIB0
K9K1216Q0C-HCB0,HIB0
Errata is added.(Front Page)-K9K12XXQ0C
tWC tWP tRC tREH tRP tREA tCEA
Specification
45 25 50 15 25 30
45
Relaxed value 60 40 60 20 40 40
55
1. Max. Thickness of TBGA packge is changed.
0.09
±0.10
(Before)
-->
1.10
±0.10
(After)
2. New definition of the number of invalid blocks is added.
(Minimum 1004 valid blocks are guaranteed for each contiguous 128Mb
memory space.)
1. The guidence of LOCKPRE pin usage is changed.
Don’t leave it N.C. Not using LOCK MECHANISM & POWER-ON AUTO-
READ, connect it Vss.(Before)
--> Not using LOCK MECHANISM & POWER-ON AUTO-READ, connect
it Vss or leave it N.C(After)
2. 2.65V device is added.
3. Note is added.
(VIL can undershoot to -0.4V and VIH can overshoot to VCC +0.4V for
durations of 20 ns or less.)
Jan. 17th 2003
Preliminary
Draft Date
Sep. 12th 2002
Jan. 3rd 2003
Remark
Advance
2.1
Mar. 5th 2003
Preliminary
2.2
Mar. 13rd 2003
2.3
Mar. 17th 2003
2.4
Apr. 4th 2003
2.5
Jul. 4th 2003
Note : For more detailed features and specifications including FAQ, please refer to Samsung’s Flash web site.
http://www.samsung.com/Products/Semiconductor/Flash/TechnicalInfo/datasheets.htm
The attached datasheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right
to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions about device. If you have
any questions, please contact the SAMSUNG branch office near you.
1
K9K1208Q0C
K9K1208D0C
K9K1208U0C
K9K1216Q0C
K9K1216D0C
K9K1216U0C
FLASH MEMORY
Document Title
64M x 8 Bit , 32M x 16 Bit NAND Flash Memory
Revision History
Revision No. History
2.6
1. tREA value of 1.8V device is changed.
K9K12XXQ0C : tREA 30ns --> 35ns
2. Errata is deleted.
1. Command table is edited.
2. AC parameters are changed.
tWC tWH tWP tRC tREH tRP tREA tCEA
K9K12XXU0C
K9K12XXD0C 50 15 25 50 15 25 30
45
K9K12XXQ0C
2.8
60
20
40
60
20
40
40
55
Dec. 17th. 2003
Draft Date
Aug. 20th. 2003
Remark
2.7
Oct. 28th. 2003
1. AC parameters are changed.
tWC tWH tWP tRC tREH tRP tREA tCEA
K9K1208Q0C 50 15 25 50 15 25 35
45
K9K1216Q0C 60 20 40 60 20 40 40
55
1. The Test Condition for Stand-by Currents are changed.
I
SB
1: CE=V
IH
, WP=0V/V
CC
-->> CE=V
IH
, WP=LOCKPRE=0V/V
CC
ISB2:
CE=V
CC
-0.2, WP=0V/V
CC
-->> CE=V
CC
-0.2, WP=LOCKPRE=0V/V
CC
1. NAND Flash Technical Notes is changed.
-Invalid block -> initial invalid block ( page 14 )
-Error in write or read operation ( page 15 )
-Program Flow Chart ( page 15 )
2. TBGA->FBGA
1. The flow chart to creat initial invalid block table is changed.
2.9
Apr. 22th 2004
3.0
Oct. 25th. 2004
3.1
May 6th. 2005
Note : For more detailed features and specifications including FAQ, please refer to Samsung’s Flash web site.
http://www.samsung.com/Products/Semiconductor/Flash/TechnicalInfo/datasheets.htm
The attached datasheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right
to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions about device. If you have
any questions, please contact the SAMSUNG branch office near you.
2
K9K1208Q0C
K9K1208D0C
K9K1208U0C
K9K1216Q0C
K9K1216D0C
K9K1216U0C
FLASH MEMORY
64M x 8 Bit / 32M x 16 Bit NAND Flash Memory
PRODUCT LIST.
Part Number
K9K1208Q0C-G,J
K9K1216Q0C-G,J
K9K1208D0C-G,J
K9K1216D0C-G,J
K9K1208U0C-G,J
K9K1216U0C-G,J
2.7 ~ 3.6V
2.4 ~ 2.9V
Vcc Range
1.70 ~ 1.95V
Organization
X8
X16
X8
X16
X8
X16
FBGA
PKG Type
FEATURES
•
Voltage Supply
- 1.8V device(K9K12XXQ0C) : 1.70~1.95V
- 2.65V device(K9F12XXD0C) : 2.4~2.9V
- 3.3V device(K9K12XXU0C) : 2.7 ~ 3.6 V
•
Organization
- Memory Cell Array
- X8 device(K9K1208X0C) : (64M + 2048K)bit x 8 bit
- X16 device(K9K1216X0C) : (32M + 1024 K)bit x 16bit
- Data Register
- X8 device(K9K1208X0C) : (512 + 16)bit x 8bit
- X16 device(K9K1216X0C) : (256 + 8)bit x16bit
•
Automatic Program and Erase
- Page Program
- X8 device(K9K1208X0C) : (512 + 16)Byte
- X16 device(K9K1216X0C) : (256 + 8)Word
- Block Erase :
- X8 device(K9K1208X0C) : (16K + 512)Byte
- X16 device(K9K1216X0C) : ( 8K + 256)Word
•
Page Read Operation
- Page Size
- X8 device(K9K1208X0C) : (512 + 16)Byte
- X16 device(K9K1216X0C) : (256 + 8)Word
- Random Access
: 10µs(Max.)
- Serial Page Access : 50ns(Min.)*
*K9K1216Q0C : 60ns(Min.)
•
Fast Write Cycle Time
- Program time : 200µs(Typ.)
- Block Erase Time : 2ms(Typ.)
•
Command/Address/Data Multiplexed I/O Port
•
Hardware Data Protection
- Program/Erase Lockout During Power Transitions
•
Reliable CMOS Floating-Gate Technology
- Endurance
: 100K Program/Erase Cycles
- Data Retention : 10 Years
•
Command Register Operation
•
Intelligent Copy-Back
•
Unique ID for Copyright Protection
•
Package
- K9K12XXX0C-GCB0/GIB0
63- Ball FBGA ( 9 x 11 /0.8mm pitch , Width 1.2 mm)
- K9K12XXX0C-JCB0/JIB0
63- Ball FBGA ( 9 x 11 /0.8mm pitch , Width 1.2 mm)
- Pb-free Package
GENERAL DESCRIPTION
Offered in 64Mx8bit or 32Mx16bit, the K9K12XXX0C is 512M bit with spare 16M bit capacity. The device is offered in 1.8V, 2.65V,
3.3V Vcc. Its NAND cell provides the most cost-effective solutIon for the solid state mass storage market. A program operation can
be performed in typical 200µs on the 528-byte(X8 device) or 264-word(X16 device) page and an erase operation can be performed
in typical 2ms on a 16K-byte(X8 device) or 8K-word(X16 device) block. Data in the page can be read out at 50ns(K9K1216Q0C :
60ns) cycle time per byte (X8 device) or word(X16 device). The I/O pins serve as the ports for address and data input/output as well
as command input. The on-chip write control automates all program and erase functions including pulse repetition, where required,
and internal verification and margining of data. Even the write-intensive systems can take advantage of the K9K12XXX0C′s extended
reliability of 100K program/erase cycles by providing ECC(Error Correcting Code) with real time mapping-out algorithm.
The K9K12XXX0C is an optimum solution for large nonvolatile storage applications such as solid state file storage and other portable
applications requiring non-volatility.
3
K9K1208Q0C
K9K1208D0C
K9K1208U0C
K9K1216Q0C
K9K1216D0C
K9K1216U0C
X8
4
FLASH MEMORY
X16
4
PIN CONFIGURATION (FBGA)
K9K12XXX0C-GCB0,JCB0/GIB0,JIB0
5
6
N.C N.C
N.C N.C
/WP
NC
NC
NC
NC
NC
NC
Vss
ALE
/RE
NC
NC
NC
I/O0
I/O1
I/O2
Vss
CLE
NC
NC
NC
NC
NC
/CE
NC
NC
NC
NC
NC
/WE
NC
NC
NC
R/B
NC
NC
NC
1
N.C N.C
2
3
1
N.C N.C
2
3
5
6
N.C N.C
N.C N.C
A
B
C
N.C
A
B
C
N.C
/WP
NC
NC
NC
NC
ALE
/RE
NC
NC
NC
Vss
CLE
NC
NC
NC
/CE
NC
NC
NC
I/O5
/WE
NC
NC
NC
R/B
NC
NC
NC
D
E
F
G
H
D
E
F
G
H
NC LOCKPRE
NC
Vcc
I/O7
Vss
I/O7 LOCKPRE
Vcc
I/O8 I/O1 I/O10 I/O12 IO14
I/O0
Vss
VccQ I/O5
I/O6
I/O9 I/O3 VccQ I/O6 I/O15
I/O2 I/O11 I/O4 I/O13 Vss
I/O3 I/O4
N.C N.C
N.C N.C
N.C N.C
N.C N.C
N.C N.C
N.C N.C
N.C N.C
N.C N.C
PACKAGE DIMENSIONS
(Top View)
(Top View)
63-Ball FBGA (measured in millimeters)
Top View
Bottom View
9.00
±0.10
0.80 x9= 7.20
0.80 x5= 4.00
9.00
±0.10
(Datum A)
A
6
0.80
5 4
3
2
1
B
#A1
A
B
0.80 x11= 8.80
0.80 x7= 5.60
2.00
9.00
±0.10
0.45
±0.05
0.25
(Min.)
(Datum B)
C
D
E
0.80
11.00
±0.10
2.80
F
G
H
63-∅0.45
±0.05
∅
0.20
M
A B
0.10MAX
4
1.20
(Max.)
Side View
11.00
±0.10
K9K1208Q0C
K9K1208D0C
K9K1208U0C
K9K1216Q0C
K9K1216D0C
K9K1216U0C
FLASH MEMORY
PIN DESCRIPTION
Pin Name
I/O
0
~ I/O
7
(K9K1208X0C)
I/O
0
~ I/O
15
(K9K1216X0C)
Pin Function
DATA INPUTS/OUTPUTS
The I/O pins are used to input command, address and data, and to output data during read operations. The I/
O pins float to high-z when the chip is deselected or when the outputs are disabled.
I/O8 ~ I/O15 are used only in X16 organization device. Since command input and address input are x8 oper-
ation, I/O8 ~ I/O15 are not used to input command & address. I/O8 ~ I/O15 are used only for data input and
output.
COMMAND LATCH ENABLE
The CLE input controls the activating path for commands sent to the command register. When active high,
commands are latched into the command register through the I/O ports on the rising edge of the WE signal.
ADDRESS LATCH ENABLE
The ALE input controls the activating path for address to the internal address registers. Addresses are
latched on the rising edge of WE with ALE high.
CHIP ENABLE
The CE input is the device selection control. When the device is in the Busy state, CE high is ignored, and
the device does not return to standby mode in program or erase operation. Regarding CE control during
read operation, refer to ’Page read’ section of Device operation .
READ ENABLE
The RE input is the serial data-out control, and when active drives the data onto the I/O bus. Data is valid
tREA after the falling edge of RE which also increments the internal column address counter by one.
WRITE ENABLE
The WE input controls writes to the I/O port. Commands, address and data are latched on the rising edge of
the WE pulse.
WRITE PROTECT
The WP pin provides inadvertent write/erase protection during power tra nsitions. The internal high voltage
generator is reset when the WP pin is active low. When LOCKPRE is a logic high and WP is a logic low, the
all blocks go to lock state.
READY/BUSY OUTPUT
The R/B output indicates the status of the device operation. When low, it indicates that a program, erase or
random read operation is in process and returns to high state upon completion. It is an open drain output and
does not float to high-z condition when the chip is deselected or when outputs are disabled.
OUTPUT BUFFER POWER
Vcc
Q
is the power supply for Output Buffer.
Vcc
Q
is internally connected to Vcc, thus should be biased to Vcc.
POWER
V
CC
is the power supply for device.
GROUND
NO CONNECTION
Lead is not internally connected.
DO NOT USE
Leave it disconnected
LOCK MECHANISM & POWER-ON AUTO-READ ENABLE
To Enable and disable the Lock mechanism and Power On Auto Read. When LOCKPRE is a logic high,
Block Lock mode and Power-On Auto-Read mode are enabled, and when LOCKPRE is a logic low, Block
Lock mode and Power-On Auto-Read mode are disabled. Power-On Auto-Read mode is available only on
3.3V device(K9K12XXU0C)
Not using LOCK MECHANISM & POWER-ON AUTO-READ, connect it Vss or leave it N.C
CLE
ALE
CE
RE
WE
WP
R/B
Vcc
Q
Vcc
Vss
N.C
DNU
LOCKPRE
NOTE
: Connect all V
CC
and V
SS
pins of each device to common power supply outputs.
Do not leave V
CC
or V
SS
disconnected.
5
FPGA/CPLD
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