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ICS8MG3-125.000AJI

Description
Oscillator
CategoryPassive components    oscillator   
File Size124KB,5 Pages
ManufacturerIDT (Integrated Device Technology)
Download Datasheet Parametric View All

ICS8MG3-125.000AJI Overview

Oscillator

ICS8MG3-125.000AJI Parametric

Parameter NameAttribute value
Is it lead-free?Lead free
Is it Rohs certified?incompatible
MakerIDT (Integrated Device Technology)
Reach Compliance Codeunknown
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS8M
X
3
LVPECL C
LOCK
O
SCILLATOR
nOUT
OUT
V
DD
ICS8M
X
3
L
OW
J
ITTER
, H
IGH
F
REQUENCY
XTAL O
SCILLATOR
Stable, ultra low jitter, LVPECL clock generation
For Gigabit Ethernet, Fibre Channel, PCI-Express™, other applications
Clock output frequencies from 75MHz to 750MHz
One differential LVPECL clock output
Output Enable (OE) pin (high impedance – when low)
Small 6-pin 5mm x 7mm x 1.5mm SMT ceramic package
Low profile package allows back-side PCB mounting
Pb-free RoHS compliant (by default; no additional code required)
3.3V or 2.5V device power supply options
Commercial (0 to +70
O
C) and Industrial (-40 to +85
O
C) temperatures
Frequency stability of ±50ppm or ±100ppm
(including initial accuracy, operating temperature variation, supply voltage
variation, load variation, reflow drift, and aging for 10 years)
5
6
8Mx3
(Top View)
1
2
• Low phase jitter < 1 ps rms maximum (12kHz to 20MHz)
6-pin CERHERMETIC 5mm x 7mm x 1.5mm SMT
E
LECTRICAL
S
PECIFICATIONS
Unless stated otherwise, V
CC
= 3.3V ± 5% or 2.5V ± 5%, T
A
= 0°C to +70°C (commercial), T
A
= -40°C to +85°C (industrial)
Specifications
Item
DC Characteristics
Power Supply
Power Supply Voltage
(V
CC
, V
EE
pins)
Power Supply Current
Current w/Output Disabled
Input Capacitance
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
Internal Pullup Resistor
Output High Voltage
1
Symbol
V
CC
I
EE
I
OED
C
IN
V
IH
V
IL
I
IH
I
IL
R
PULLUP
V
OH
V
OL
V
SWSING
Min.
3.135
2.375
Typ.
3.3
2.5
75
4
Max.
3.465
2.625
<0.6
Units
V
V
mA
mA
pF
V
V
µA
µA
V
V
V
Test Conditions
3.3V operation
2.5V operation (8MJ3 and 8MK3 only)
OE = V
CC
OE = V
EE
Output Enable
(OE pin)
LVCMOS/LVTTL
0.7 * V
CC
0.3 * V
CC
5
-150
51
V
CC
- 1.4
V
CC
- 2.0
0.6
75
V
CC
- 0.9
V
CC
- 1.7
1.0
750
±100
±50
50
600
600
10
<1
V
CC
= V
IN
= 3.465V or 2.625V
V
CC
= 3.465V or 2.625V, V
IN
= 0V
Outputs terminated with 50
Ω
to V
CC
- 2V.
See Parameter Measurement Information,
Output Load AC Test Circuit diagrams.
See Parameter Measurement Information,
Output Rise/Fall Time diagram
Clock Output
Level
(OUT, nOUT)
LVPECL
Output Low Voltage
1
Peak-to-Peak Output
Voltage Swing
AC Characteristics
Output
Output Frequency Range
(OUT, nOUT)
Frequency Stability Error
Output Duty Cycle
Output Rise Time
Output Fall Time
Oscillator Star t-up Time
RMS Phase Jitter, Random
2
Jitter
Δ
f/f
O
odc
t
R
t
F
t
OSC
t
jit (Ø)
t
DS3
t
RS3
t
RMS3
t
P-P3
0.2
3
3
25
3
t
acc
4
NOTE 1: Outputs terminated with 50
Ω
to V
CC
- 2V. See Parameter Measurement Information,
NOTE 2: Measured using an Aeroflex PN9500 with a 12kHz to 20MHz integration range.
NOTE 3: Measured using a Wavecrest SIA-3000.
MHz
All conditions
ppm p-p 8MH3 & 8MK3 Includes frequency set, V
CC
, T
A
and
ppm p-p 8MG3 & 8MJ3 load variation, reflow drift, 10 yr. aging
%
See Output Duty Cycle Diagram
ps
and Rise/Fall Time Diagram in
20% to 80%
of V
OH
- V
OL
Parameter Measurement Information
ps
ms
Time at Min. V
CC
(3.135V or 2.375V) to be 0s
ps rms design target
ps
Deterministic
ps
Random,
σ
of random jitter
ps
Root Mean Square,
σ
of total jitter distribution
ps
Peak-to-Peak
ps
Accumulated Jitter, n = 2 to 50,000 cycles
Output Load AC Test Circuit diagrams.
Supply Voltage & Frequency Accuracy
G=
H=
J=
K=
8Mx3AJ
3.3V / 3.3V
3.3V / 3.3V
2.5V / 3.3V
2.5V / 3.3V
±50 ppm
±100 ppm
±50 ppm
±100 ppm
The Preliminary Information presented herein represents a product in prototyping or pre-production. The
noted characteristics are based on initial product characterization. Integrated Circuit Systems, Incorpo-
rated (ICS) reserves the right to change any circuitry or specifications without notice.
www.icst.com/products/hiperclocks.html
1
GND
REV. B FEBRUARY 10, 2006
OE
NC
3
4

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