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IBM11N4845BB-6RJ

Description
EDO DRAM Module, 4MX72, 60ns, CMOS, DIMM-168
Categorystorage    storage   
File Size331KB，29 Pages
ManufacturerIBM
Websitehttp://www.ibm.com
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IBM11N4845BB-6RJ Overview

EDO DRAM Module, 4MX72, 60ns, CMOS, DIMM-168

IBM11N4845BB-6RJ Parametric

Parameter NameAttribute value
MakerIBM
Parts packaging codeDIMM
package instruction,
Contacts168
Reach Compliance Codeunknown
ECCN codeEAR99
access modeFAST PAGE WITH EDO
Maximum access time60 ns
Other featuresRAS ONLY/CAS BEFORE RAS/HIDDEN REFRESH
JESD-30 codeR-XDMA-N168
memory density301989888 bit
Memory IC TypeEDO DRAM MODULE
memory width72
Number of functions1
Number of ports1
Number of terminals168
word count4194304 words
character code4000000
Operating modeASYNCHRONOUS
organize4MX72
Output characteristics3-STATE
Package body materialUNSPECIFIED
Package shapeRECTANGULAR
Package formMICROELECTRONIC ASSEMBLY
Certification statusNot Qualified
refresh cycle2048
Maximum supply voltage (Vsup)3.45 V
Minimum supply voltage (Vsup)3.15 V
Nominal supply voltage (Vsup)3.3 V
surface mountNO
technologyCMOS
Terminal formNO LEAD
Terminal locationDUAL

IBM11N4845BB-6RJ Preview

IBM11M4730C4M x 72 E12/10, 5.0V, Au.
Preliminary
Features
• 168 Pin JEDEC Standard, Unbuffered 8 Byte Dual
In-line Memory Module
• 4Mx72 Extended Data Out Page Mode DIMM
S
• Performance:
-6R
t
RAC
t
CAC
t
AA
t
RC
t
HPC
RAS Access Time
CAS Access Time
Access Time From Address
Cycle Time
EDO Mode Cycle Time
60ns
18ns
30ns
104ns
25ns
IBM11N4845BB
IBM11N4845CB
4M x 72 Super EOS Module
• System Performance Benefits:
-Non buffered for increased performance
-Reduced noise (35 VSS/VCC pins)
-Serial PDs
• Extended Data Out (EDO) Mode, Read-Modify-Write
Cycles
• Refresh Modes: RAS-Only, CBR and Hidden Refresh
• 2048 refresh cycles distributed across 32ms (11/11
addressing)
• 4096 refresh cycles distributed across 64ms (12/10
addressing)
• 11/11 or 12/10 addressing (Row/Column)
• Card size: 5.25" x 1.2" x 0.354"
• DRAMS in SOJ Package
• Au contacts
• All inputs and outputs are LVTTL (3.3V) compatible
• Single 3.3V
±
0.15V Power Supply
• Optimized for ECC applications
• Provides Chip-Kill (ECC) protection transparently to
an existing Single Error Correction (SEC) system
Description
The IBM11N4845BB and IBM11N4845CB are industry
standard 168-pin 8-byte Dual In-line Memory Modules
(DIMMs) which are organized as a 4Mx72 high speed
memory array supporting EDO applications. The DIMM
uses 18 4Mx4 EDO DRAMs in SOJ packages along with
an ASIC and check bit DRAMs to provide an SEC ECC
system with transparent chip kill protection.
The DIMMs use serial presence detects implemented via
a serial EEPROM using the two pin I
2
C protocol. This
communication protocol uses Clock (SCL) and Data I/O
(SDA) lines to synchronously clock data between the
master (system logic) and the slave EEPROM device
(DIMM). The EEPROM device address pins (SA0-2) are
brought out to the DIMM tabs to allow 8 unique
DIMM/EEPROM addresses. The first 128 bytes are uti-
lized by the DIMM manufacturer and the second 128
bytes of serial PD data are available to the customer.
All IBM 168-pin DIMMs provide a high performance, flexi-
ble 8-byte interface in a 5.25” long space-saving footprint.
Related products include the buffered DIMMs (x64, x72
parity and x72 ECC Optmized) for applications which can
benefit from the on-card buffers.
Card Outline
(Front)
(Back)
1
85
10 11
94 95
40 41
124 125
84
168
75H5485
GA14-4640-00
Revised 11/96
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 1 of 28
IBM11N4845BB
IBM11N4845CB
4M x 72 Super EOS Module
Preliminary
Pin Description
RAS0, RAS2
CAS0 - CAS7
WE0, WE2
OE0, OE2
A0 - A11
DQx
CBx
Row Address Strobe
Column Address Strobe
Read/write Input
Output Enable
Address Inputs
Data Input/Output
Check Bit Data Input/Output
V
CC
V
SS
NC
DU
SCL
SDA
SA0-2
Power (3.3V)
Ground
No Connect
Don’t Use
Serial Presence Detect Clock Input
Serial Presence Detect Data Input
Serial Presence Detect Address Inputs
Pinout
Pin#
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
Front
Side
V
SS
DQ0
DQ1
DQ2
DQ3
V
CC
DQ4
DQ5
DQ6
DQ7
DQ8
V
SS
DQ9
DQ10
DQ11
DQ12
DQ13
V
CC
DQ14
DQ15
CB0
Pin#
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
Back
Side
V
SS
DQ32
DQ33
DQ34
DQ35
V
CC
DQ36
DQ37
DQ38
DQ39
DQ40
V
SS
DQ41
DQ42
DQ43
DQ44
DQ45
V
CC
DQ46
DQ47
CB4
Pin#
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
Front
Side
CB1
V
SS
NC
NC
V
CC
WE0
CAS0
CAS1
RAS0
OE0
V
SS
A0
A2
A4
A6
A8
A10
NC
V
CC
V
CC
DU
Pin#
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
Back
Side
CB5
V
SS
NC
NC
V
CC
DU
CAS4
CAS5
NC
DU
V
SS
A1
A3
A5
A7
A9
A11
NC
V
CC
DU
DU
Pin#
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
Front
Side
V
SS
OE2
RAS2
CAS2
CAS3
WE2
V
CC
NC
NC
CB2
CB3
V
SS
DQ16
DQ17
DQ18
DQ19
V
CC
DQ20
NC
DU
NC
Pin#
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
Back
Side
V
SS
DU
NC
CAS6
CAS7
DU
V
CC
NC
NC
CB6
CB7
V
SS
DQ48
DQ49
DQ50
DQ51
V
CC
DQ52
NC
DU
NC
Pin#
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
Front
Side
V
SS
DQ21
DQ22
DQ23
V
SS
DQ24
DQ25
DQ26
DQ27
V
CC
DQ28
DQ29
DQ30
DQ31
V
SS
NC
NC
NC
SDA
SCL
V
CC
Pin#
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
Back
Side
V
SS
DQ53
DQ54
DQ55
V
SS
DQ56
DQ57
DQ58
DQ59
V
CC
DQ60
DQ61
DQ62
DQ63
V
SS
NC
NC
SA0
SA1
SA2
V
CC
Note:
All pin assignments are consistent for all 8 Byte unbuffered versions.
Ordering Information
Part Number
IBM11N4845BB-6RJ
IBM11N4845CB-6RJ
4Mx72
6Rns
12/10
Organization
Speed
Addr.
11/11
Au
5.25”x1.2”x 0.354”
3.3V
Leads
Dimension
Power
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
75H5485
GA14-4640-00
Revised 11/96
Page 2 of 28
Preliminary
IBM11N4845BB
IBM11N4845CB
4M x 72 Super EOS Module
x72 ECC DIMM Block Diagram (1 Bank, x4 DRAMs)
RAS CAS0
CAS1 ...
ASIC
CAS7
WE OE
DQ0
DQ1
DQ2
DQ3 Byte 0
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11 Byte 1
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
4
MDQ0-3
CAS0
DRAMs
MDQ4-7
4
CAS1
DRAMs
MDQ8-11
4
MDQ12-15
4
MDQ16-19
CAS2
DRAMs
MDQ20-23
4
4
CAS 3 - 7
DRAMs
Bytes 2 - 7
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
Check Bits
Dlyd WE, OE, CAS
Modes POR
Test Cntl
SERIAL PD
SCL
A0
SA0
A1
SA1
A2
SA2
SDA
A0-AN
V
CC
V
SS
A0 - AN: DRAMS D0 - D17
D0 - D17
D0 - D17
75H5485
GA14-4640-00
Revised 11/96
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 3 of 28
IBM11N4845BB
IBM11N4845CB
4M x 72 Super EOS Module
Preliminary
Truth Table
Function
Standby
Read
Early-Write
Late-Write
RMW
EDO Page Mode - Read 1st Cycle
Subsequent Cycles
EDO Page Mode - Write 1st Cycle
Subsequent Cycles
EDO Page Mode - RMW 1st Cycle
Subsequent Cycles
RAS-Only Refresh
CAS-Before-RAS Refresh
Read
Hidden Refresh
Write
L→H→L
L
H
X
Row
Col
Data In
RAS
H
L
L
L
L
L
L
L
L
L
L
L
H→L
L→H→L
CAS
H→X
L
L
L
L
H→L
H→L
H→L
H→L
H→L
H→L
H
L
L
WE
X
H
L
H→L
H→L
H
H
L
L
H→L
H→L
X
H
H
OE
X
L
X
H
L→H
L
L
X
X
L→H
L→H
X
X
L
Row
Address
X
Row
Row
Row
Row
Row
N/A
Row
N/A
Row
N/A
Row
X
Row
Column
Address
X
Col
Col
Col
Col
Col
Col
Col
Col
Col
Col
N/A
X
Col
DQx
High Impedance
Valid Data Out
Valid Data In
Valid Data In
Valid Data In/Out
Valid Data Out
Valid Data Out
Valid Data In
Valid Data In
Valid Data In/Out
Valid Data In/Out
High Impedance
High Impedance
Data Out
Serial Presence Detect
SPD Entry
Byte #
0
1
2
3
Description
Number of SPD Bytes
Total # Bytes in Serial PD
Memory Type
# of Row Addresses
SPD Entry
Value
128
256
EDO
11
12
11
10
1
x72
0
LVTTL
60ns
18ns
x72
60
18
ECC
Normal 15.6
µs
Binary
Bit 7
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit 6
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
Bit5
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
Bit4
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
Bit3
0
1
0
1
1
1
1
0
1
0
0
1
0
0
0
0
0
Bit2
0
0
0
0
1
0
0
0
0
0
0
1
0
0
0
1
1
Bit1
0
0
1
1
0
1
1
0
0
0
0
0
1
1
0
0
0
Bit0
0
0
0
1
0
1
0
1
0
0
1
0
0
0
0
0
0
Hex
80
08
02
0B
0C
0B
0A
01
48
00
01
3C
12
02
00
04
04
4
5
6
7
8
9
10
11
12
13
14
# of Column Addresses
# of DIMM Banks
Module Data Width
Module Data Width (Cont.)
Module Interface Levels
RAS Access
CAS Access
Dimm Config(Error Det/Corr.)
Refresh Rate/Type
Primary DRAM Organization
Secondary DRAM Organization
x4
x4
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
75H5485
GA14-4640-00
Revised 11/96
Page 4 of 28
Preliminary
IBM11N4845BB
IBM11N4845CB
4M x 72 Super EOS Module
Absolute Maximum Ratings
Symbol
V
CC
V
IN
V
IN/OUT
(SPD)
V
OUT
T
CASE
T
STG
P
D
I
OUT
Parameter
Power Supply Voltage
Input Voltage
Input Voltage (Serial PD Device)
Output Voltage
Operating Temperature of ASIC case
Storage Temperature
Rating (3.3V)
-0.5 to +4.6
-0.5 to min (V
CC
+ 0.5, 4.6)
-0.3 to +6.5
-0.5 to min (V
CC
+ 0.5, 4.6)
0 to +70
-55 to +125
11/11 Addressing
Power Dissipation
Short Circuit Output Current
x72
6.5
50
12/10 Addressing
5.7
mA
1
Units
V
V
V
V
Notes
1
1
1
1
1
1
1, 2
°
C
°
C
W
1. Stresses greater than those listed may cause permanent damage to the device. This is a stress rating only and functional opera-
tion of the device at these or any other conditions above those indicated is not implied. Exposure to absolute maximum rating con-
dition for extended periods may affect reliability.
2. Worst case power dissipation is for legal operation of DRAMs with the outputs open.
Recommended DC Operating Conditions
(T
C
= 0 to 60
°
C)
3.3V
Symbol
V
CC
V
IH
V
IL
Parameter
Supply Voltage
Input High Voltage
Input Low Voltage
Min
3.15
2.0
-0.5
Typ
3.3
—
—
Max
3.45
V
CC
+ 0.5
0.8
Units
V
V
V
Notes
1
1, 2
1, 2
1. All voltages referenced to V
SS.
2. V
IH
may overshoot to V
CC
+ 1.2V for pulse widths of
≤
4.0ns (or V
CC
+ 1.0V for
≤
8.0ns). Additionally, V
IL
may undershoot to -2.0V
for pulse widths
≤
4.0ns (or -1.0V for
≤
8.0ns). Pulse widths measured at 50% points with amplitude measured peak to DC refer-
ence.
Capacitance
(T
C
= 0 to +60
°
C, V
CC
= 3.3V
±
0.15V)
Max
Symbol
C
I1
C
I2
C
I3
C
I4
C
I5
C
IO1
C
IO2
Input Capacitance (A0-A11)
Input Capacitance (RAS)
Input Capacitance (CAS)
Input Capacitance (SCL, SA0-3)
Input Capacitance (WE, OE)
Input/Output Capacitance (DQ
X
, CB
X
)
Input/Output Capacitance (SDA)
Parameter
x72
120
85
30
8
15
11
10
Units
pF
pF
pF
pF
pF
pF
pF
75H5485
GA14-4640-00
Revised 11/96
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 5 of 28
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IBM11N4845BB-6RJ Related Products

IBM11N4845BB-6RJ IBM11N4845CB-6RJ
Description EDO DRAM Module, 4MX72, 60ns, CMOS, DIMM-168 EDO DRAM Module, 4MX72, 60ns, CMOS, DIMM-168
Maker IBM IBM
Parts packaging code DIMM DIMM
Contacts 168 168
Reach Compliance Code unknown unknow
ECCN code EAR99 EAR99
access mode FAST PAGE WITH EDO FAST PAGE WITH EDO
Maximum access time 60 ns 60 ns
Other features RAS ONLY/CAS BEFORE RAS/HIDDEN REFRESH RAS ONLY/CAS BEFORE RAS/HIDDEN REFRESH
JESD-30 code R-XDMA-N168 R-XDMA-N168
memory density 301989888 bit 301989888 bi
Memory IC Type EDO DRAM MODULE EDO DRAM MODULE
memory width 72 72
Number of functions 1 1
Number of ports 1 1
Number of terminals 168 168
word count 4194304 words 4194304 words
character code 4000000 4000000
Operating mode ASYNCHRONOUS ASYNCHRONOUS
organize 4MX72 4MX72
Output characteristics 3-STATE 3-STATE
Package body material UNSPECIFIED UNSPECIFIED
Package shape RECTANGULAR RECTANGULAR
Package form MICROELECTRONIC ASSEMBLY MICROELECTRONIC ASSEMBLY
Certification status Not Qualified Not Qualified
refresh cycle 2048 4096
Maximum supply voltage (Vsup) 3.45 V 3.45 V
Minimum supply voltage (Vsup) 3.15 V 3.15 V
Nominal supply voltage (Vsup) 3.3 V 3.3 V
surface mount NO NO
technology CMOS CMOS
Terminal form NO LEAD NO LEAD
Terminal location DUAL DUAL

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