IDGV51-05A1F1C-45X datasheet, PDF

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IDGV51-05A1F1C-45X: DescriptionSynchronous Graphics RAM, 16MX32, CMOS, PBGA170, GREEN, PLASTIC, TFBGA-170; Categorystorage storage; File Size900KB，20 Pages; ManufacturerQIMONDA; Environmental Compliance

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IDGV51-05A1F1C-45X Overview

Synchronous Graphics RAM, 16MX32, CMOS, PBGA170, GREEN, PLASTIC, TFBGA-170

IDGV51-05A1F1C-45X Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Maker	QIMONDA
Parts packaging code	BGA
package instruction	TFBGA, BGA170,14X17,32
Contacts	170
Reach Compliance Code	unknown
ECCN code	EAR99
access mode	MULTI BANK PAGE BURST
Other features	AUTO/SELF REFRESH
Spare memory width	16
I/O type	COMMON
JESD-30 code	R-PBGA-B170
length	14 mm
memory density	536870912 bit
Memory IC Type	SYNCHRONOUS GRAPHICS RAM
memory width	32
Number of functions	1
Number of ports	1
Number of terminals	170
word count	16777216 words
character code	16000000
Operating mode	SYNCHRONOUS
Maximum operating temperature	85 °C
Minimum operating temperature
organize	16MX32
Output characteristics	3-STATE
Package body material	PLASTIC/EPOXY
encapsulated code	TFBGA
Encapsulate equivalent code	BGA170,14X17,32
Package shape	RECTANGULAR
Package form	GRID ARRAY, THIN PROFILE, FINE PITCH
power supply	1.5 V
Certification status	Not Qualified
refresh cycle	8192
Maximum seat height	1.2 mm
self refresh	YES
Maximum supply voltage (Vsup)	1.545 V
Minimum supply voltage (Vsup)	1.455 V
Nominal supply voltage (Vsup)	1.5 V
surface mount	YES
technology	CMOS
Temperature level	OTHER
Terminal form	BALL
Terminal pitch	0.8 mm
Terminal location	BOTTOM
width	12 mm

IDGV51-05A1F1C-45X Preview

September 2008

IDGV51-05A1F1C-[40X/45X/50X]

512Mbit x32/x16 GDDR5 SGRAM

EU RoHS compliant

Internet Data Sheet

Rev. 1.10

Internet Data Sheet

IDGV51-05A1F1C

512MBit GDDR5 Graphics RAM

IDGV51-05A1F1C-[40X/45X/50X]

Revision History: 2008-09, Rev. 1.10

Page

All

Subjects (major changes since last revision)

Figure1 - Maximum data rate for RDQS mode increased to 3.0 Gbps; PLL-off mode restricted to 4.0 Gbps

36X speed bin removed

Previous Revision: Rev. 1.00, 2008-06

We Listen to Your Comments

Any information within this document that you feel is wrong, unclear or missing at all?

Your feedback will help us to continuously improve the quality of this document.

Please send your proposal (including a reference to this document) to:

techdoc@qimonda.com

qag_techdoc_A4, 4.22, 2008-07-22

11092007-TJ6A-WC0N

Internet Data Sheet

IDGV51-05A1F1C

512MBit GDDR5 Graphics RAM

1.1

Overview

Features

•

Auto Precharge option for each burst access

Programmable CAS latency: 6 to 20

Programmable Write latency: 3 to 7

Programmable CRC READ latency: 0 to 2

Programmable CRC WRITE latency: 8 to 11

Digital

RAS

lockout

RDQS mode on EDC pin

Data output mode for Vendor ID, density and FIFO depth

Low Power modes

On-chip temperature sensor with read-out

Auto refresh and self refresh modes

32ms data retention (8k cycles)

Automatic temperature sensor controlled self refresh rate

On-die termination (ODT): nom. values of 60

or 120

Pseudo open drain (POD–15) compatible outputs (40

pulldown, 60

pullup)

ODT and output driver strength auto-calibration with

external resistor ZQ pin (120

Ω)

Programmable termination and driver strength offsets

Selectable external or internal VREF for data inputs;

programmable offsets for internal VREF

Separate external VREF for address / command inputs

Boundary Scan function with SEN pin

Mirror function with MF pin

1.5V +/- 0.045 V

DDQ

1.5V +/- 0.045 V

PG-TFBGA 170

RoHS Compliant Product

• Monolithic 512Mbit GDDR5 SGRAM (2Mbit x 32 I/O x 8

banks and 4Mbit x 16 I/O x 8 banks)

• x32/x16 mode configuration set at power-up with EDC pin

• Quarter data-rate differential clock inputs CK/CK for

address and commands

• Two half data-rate differential clock inputs WCK/WCK,

each associated with two data bytes (DQ, DBI, EDC)

• Single ended interface for data, address and command

• Double Data Rate (DDR) data (WCK)

• Single Data Rate (SDR) command (CK)

• Double Data Rate (DDR) addressing (CK)

• Write data mask function (single/double byte mask) via

address bus

• 8 internal banks

• 4 bank groups for

CCD

= 3

• 8n prefetch architecture: 256 bit per array Read or Write

access

• Burst Length: 8 only

• Data bus inversion (DBI) and address bus inversion (ABI)

• Input/output PLL on/off mode

• Address training: address input monitoring via DQ pins

• WCK2CK clock training: phase information via EDC pins

• Data read and write training via Read FIFO

(FIFO depth = 5)

• Read FIFO pattern preload by LDFF command

• Direct write data load to Read FIFO by WRTR command

• Consecutive read of Read FIFO by RDTR command

• Programmable EDC hold pattern for CDR

• Read/Write data transmission integrity secured by cyclic

redundancy check (CRC–8)

1) RoHS Compliant Product: Restriction of the use of certain hazardous substances (RoHS) in electrical and electronic equipment as defined

in the directive 2002/95/EC issued by the European Parliament and of the Council of 27 January 2003. These substances include mercury,

lead, cadmium, hexavalent chromium, polybrominated biphenyls and polybrominated biphenyl ethers.

Rev. 1.10, 2008-09

11092007-TJ6A-WC0N

Internet Data Sheet

IDGV51-05A1F1C

512MBit GDDR5 Graphics RAM

TABLE 1

Ordering Information

Part Number

IDGV51-05A1F1C – 40X

IDGV51-05A1F1C – 45X

IDGV51-05A1F1C – 50X

Organization

×32

/ x16

Max. Data Rate

(Gbps/pin)

4.0

4.5

5.0

Package

PG-TFBGA 170

1) I: Qimonda Identifier, D: DRAM, GV: GDDR5, 51: 512Mbit, 0: 1 x CS, 5: x32, A1: 1st node, F1: FBGA, C: Commercial 0° - 85/95°C

1.2

Description

The Qimonda GDDR5 SGRAM is a high speed dynamic random-access memory designed for applications requiring high

bandwidth. It contains 536,870,912 bits and is internally configured as a 8-bank DRAM.

The GDDR5 SGRAM uses a 8n prefetch architecture and DDR interface to achieve high-speed operation. It can be configured

to operate in x32 mode or x16 (clamshell) mode. The mode is detected during device initialization. The GDDR5 interface

transfers two 32 bit wide data words per WCK clock cycle to/from the I/O pins. Corresponding to the 8n prefetch a single write

or read access consists of a 256 bit wide, two CK clock cycle data transfer at the internal memory core and eight corresponding

32 bit wide one-half WCK clock cycle data transfers at the I/O pins.

The GDDR5 SGRAM operates from a differential clock CK and CK. Commands are registered at every rising edge of CK.

Addresses are registered at every rising edge of CK and every rising edge of CK.

GDDR5 replaces the pulsed strobes (WDQS & RDQS) used in previous DRAMs such as GDDR4 with a free running differential

forwarded clock (WCK/WCK) with both input and output data registered and driven respectively at both edges of the forwarded

WCK.

Read and write accesses to the GDDR5 SGRAM are burst oriented; accesses start at a selected location and continue for a

total of eight data words. Accesses begin with the registration of an ACTIVE command, which is then followed by a READ or

WRITE command. The address bits registered coincident with the ACTIVE command and the next rising CK edge are used to

select the bank and the row to be accessed. The address bits registered coincident with the READ or WRITE command and

the next rising CK edge are used to select the bank and the column location for the burst access.

Rev. 1.10, 2008-09

11092007-TJ6A-WC0N

Internet Data Sheet

IDGV51-05A1F1C

512MBit GDDR5 Graphics RAM

1.3

Operating Frequency Ranges

Figure 1

provides an overview of the operating frequency ranges for PLL-on and PLL-off operation in normal and RDQS

modes.

FIGURE 1

Operating Modes and Frequency Ranges

Rev. 1.10, 2008-09

11092007-TJ6A-WC0N

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