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DS26102
16-Port Transmission
Convergence Device
www.maxim-ic.com
GENERAL DESCRIPTION
On the transmit side, the DS26102 receives ATM cells
from an ATM device through a UTOPIA II interface,
provides cell buffering (up to 4 cells), HEC generation
and insertion, cell scrambling, and converts the data
to a serial stream appropriate for interfacing to a
T1/E1 framer or transceiver. On the receive side, the
DS26102 receives a TDM stream from a T1/E1 framer
or transceiver; searches for the cell alignment; verifies
the HEC; provides cell filtering, descrambling, and cell
buffering; and passes the cells to an ATM device
through the UTOPIA II interface. Other low-level traffic
management functions are selectable for the transmit
and receive paths. The DS26102 can also be used in
fractional T1/E1 applications.
The DS26102 maps ATM cells to T1/E1 TDM frames
as per the ATM Forum Specifications af-phy-0016.000
and af-phy-0064.000. In the receive direction, the cell
delineation mechanism used for finding ATM cell
boundary within T1/E1 frame is performed as per ITU
I.432. The DS26102 provides a mapping solution for
up to 16 T1/E1 TDM ports. The terms physical layer
(PHY) and line side are used synonymously in this
document and refer to the device interfacing with the
line side of the DS26102. The terms ATM layer and
system side are used synonymously and refer to the
DS26102’s UTOPIA II interface.
FEATURES
§
§
§
§
§
§
§
§
§
§
§
§
§
§
§
§
§
§
Supports 16 T1/E1 TDM Ports
Supports Fractional T1/E1
Compliant to ATM Forum Specifications for ATM
Over T1 and E1
Standard UTOPIA II Interface to the ATM Layer
Configurable UTOPIA Address Range
Configurable Tx FIFO Depth to 2, 3, or 4 Cells
Optional Payload Scrambling in Transmit
Direction and Descrambling in Receive Direction
per ITU I.432
Optional HEC Insertion in Transmit Direction with
Programmable COSET Polynomial Addition
HEC-Based Cell Delineation
Single-Bit HEC Error Correction in the Receive
Direction
Receive HEC-Errored Cell Filtering
Receive Idle/Unassigned Cell Filtering
User-Definable Cell Filtering
8-Bit Mux/Nonmux, Motorola/Intel Microprocessor
Interface
Internal Clock Generator Eliminates External
High-Speed Clocks
Internal One-Second Timer
Detects/Reports Up to Eight External Status
Signals with Interrupt Support
IEEE 1149.1 JTAG Boundary Scan Support
17mm x 17mm, 256-Pin CSBGA
§
FUNCTIONAL DIAGRAM
Features continued on page 5.
APPLICATIONS
DSLAMS
ATM Over T1/E1
Routers
IMA
16 TDM
PORTS
DS26102
UTOPIA II
ORDERING INFORMATION
PART
DS26102
TEMP RANGE
-40°C to +85°C
PIN-PACKAGE
256 CSBGA
Note:
Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device
may be simultaneously available through various sales channels. For information about device errata, click here:
www.maxim-ic.com/errata.
1 of 64
REV: 032805
DS26102 16-Port Transmission Convergence Device
TABLE OF CONTENTS
1.
2.
3.
4.
5.
6.
FEATURES ......................................................................................................................................5
APPLICABLE STANDARDS............................................................................................................5
ACRONYMS AND DEFINITIONS.....................................................................................................6
BLOCK DIAGRAM ...........................................................................................................................7
PIN DESCRIPTION ..........................................................................................................................8
SIGNAL DEFINITIONS...................................................................................................................12
6.1
6.2
6.3
TDM S
IGNALS
..........................................................................................................................12
UTOPIA-S
IDE
S
IGNALS
............................................................................................................12
M
ICROPROCESSOR AND
S
YSTEM
I
NTERFACE
S
IGNALS
................................................................14
6.4
T
EST AND
JTAG S
IGNALS
.........................................................................................................16
7. TRANSMIT OPERATION ...............................................................................................................17
7.1
7.2
7.3
UTOPIA-S
IDE
T
RANSMIT
—M
UXED
M
ODE WITH
1 TXCLAV ........................................................17
UTOPIA-S
IDE
T
RANSMIT
—D
IRECT
S
TATUS
M
ODE
(MULTITXCLAV) .........................................19
T
RANSMIT
P
ROCESSING
............................................................................................................20
7.4
P
HYSICAL
-S
IDE
T
RANSMIT
.........................................................................................................21
8. RECEIVE OPERATION..................................................................................................................23
8.1
8.2
8.3
P
HYSICAL
-S
IDE
R
ECEIVE
...........................................................................................................23
R
ECEIVE
P
ROCESSING
..............................................................................................................25
UTOPIA-S
IDE
R
ECEIVE
—M
UXED
M
ODE WITH
1 RXCLAV..........................................................27
8.4
UTOPIA-S
IDE
R
ECEIVE
—D
IRECT
S
TATUS
M
ODE
(MULTIRXCLAV) ...........................................28
9. REGISTER MAPPING....................................................................................................................30
10. REGISTER DEFINITIONS..............................................................................................................31
10.1
10.2
T
RANSMIT
R
EGISTERS
..............................................................................................................31
S
TATUS
R
EGISTERS
..................................................................................................................35
10.3 R
ECEIVE
R
EGISTERS
................................................................................................................36
11. JTAG BOUNDARY SCAN ARCHITECTURE AND TEST ACCESS PORT....................................45
11.1
I
NSTRUCTION
R
EGISTER
............................................................................................................48
11.2 T
EST
R
EGISTERS
......................................................................................................................49
12. OPERATING PARAMETERS.........................................................................................................52
13. CRITICAL TIMING INFORMATION................................................................................................53
14. THERMAL INFORMATION ............................................................................................................59
15. APPLICATIONS INFORMATION ...................................................................................................60
15.1
15.2
A
PPLICATION IN
ATM U
SER
-N
ETWORK
I
NTERFACES
...................................................................60
I
NTERFACING WITH
F
RAMERS
....................................................................................................60
15.3 F
RACTIONAL
T1/E1 S
UPPORT
...................................................................................................61
16. PACKAGE INFORMATION............................................................................................................62
17. REVISION HISTORY......................................................................................................................64
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DS26102 16-Port Transmission Convergence Device
TABLE OF FIGURES
Figure 4-1. Block Diagram ....................................................................................................................... 7
Figure 7-1. Polling Phase and Selection Phase at Transmit Interface.....................................................18
Figure 7-2. End and Restart of Cell at Transmit Interface .......................................................................18
Figure 7-3. Transmission to PHY Paused for Three Cycles ....................................................................19
Figure 7-4. Example of Direct Status Indication, Transmit Direction .......................................................20
Figure 7-5. Transmit Cell Flow and Processing ......................................................................................21
Figure 7-6. Transmit Framer Interface in TFP Mode for T1.....................................................................22
Figure 7-7. Transmit Framer Interface in Gapped-Clock Mode for T1.....................................................22
Figure 7-8. Transmit Framer Interface in TFP Mode for E1.....................................................................22
Figure 7-9. Transmit Framer Interface in Gapped-Clock Mode for E1.....................................................23
Figure 8-1. Receive Framer Interface in RFP Mode for T1 .....................................................................24
Figure 8-2. Receive Framer Interface in Gapped-Clock Mode for T1......................................................24
Figure 8-3. Receive Framer Interface in RFP Mode for E1 .....................................................................25
Figure 8-4. Receive Framer Interface in Gapped-Clock Mode for E1......................................................25
Figure 8-5. Cell Delineation State Diagram.............................................................................................26
Figure 8-6. Header Correction State Machine.........................................................................................26
Figure 8-7. Polling Phase and Selection at Receive Interface.................................................................27
Figure 8-8. End and Restart of Cell Transmission at Receive Interface ..................................................28
Figure 8-9. Example Direct Status Indication, Receive Direction ............................................................29
Figure 10-1. Accessing Tx PMON Counter.............................................................................................34
Figure 10-2. Accessing Rx PMON Counters...........................................................................................40
Figure 11-1. JTAG Functional Block Diagram.........................................................................................45
Figure 11-2. TAP Controller State Diagram ............................................................................................47
Figure 13-1. Intel Bus Read Timing (BTS = 0/MUX = 1) .........................................................................53
Figure 13-2. Intel Bus Write Timing (BTS = 0/MUX = 1) .........................................................................54
Figure 13-3. Motorola Bus Timing (BTS = 1/MUX = 1)............................................................................54
Figure 13-4. Intel Bus Read Timing (BTS = 0/MUX = 0) .........................................................................55
Figure 13-5. Intel Bus Write Timing (BTS = 0/MUX = 0) .........................................................................56
Figure 13-6. Motorola Bus Read Timing (BTS = 1/MUX = 0) ..................................................................56
Figure 13-7. Motorola Bus Write Timing (BTS = 1/MUX = 0) ..................................................................56
Figure 13-8. Setup/Hold Time Definition .................................................................................................58
Figure 13-9. Delay Time Definition .........................................................................................................58
Figure 13-10. JTAG Interface Timing Diagram .......................................................................................58
Figure 15-1. User-Network Interface Application ....................................................................................60
Figure 15-2. DS26102 Interfacing with Dallas Framer in Framing-Pulse Mode .......................................61
3 of 64
DS26102 16-Port Transmission Convergence Device
LIST OF TABLES
Table 5-A. Pin Description List ................................................................................................................ 8
Table 9-A. Register Map.........................................................................................................................30
Table 11-A. Instruction Codes for IEEE 1149.1 Architecture...................................................................48
Table 11-B. ID Code Structure ...............................................................................................................48
Table 11-C. Device ID Codes .................................................................................................................48
Table 11-D. Boundary Scan Control Bits ................................................................................................49
Table 13-A. AC Characteristics—Multiplexed Parallel Port (MUX = 1)....................................................53
Table 13-B. AC Characteristics—Nonmultiplexed Parallel Port (MUX = 1) .............................................55
Table 13-C. Framer Interface AC Characteristics ...................................................................................57
Table 13-D. UTOPIA Transmit AC Characteristics .................................................................................57
Table 13-E. UTOPIA Receive AC Characteristics...................................................................................57
Table 13-F. JTAG Interface Timing.........................................................................................................58
Table 13-G. System Clock AC Characteristics........................................................................................59
Table 14-A. Thermal Properties, Natural Convection..............................................................................59
Table 14-B. Theta-JA (q
JA
) vs. Airflow.....................................................................................................59
Table 15-A. Suggested Clock Edge Configurations ................................................................................61
Table 15-B. Fractional T1/E1 Register Settings ......................................................................................61
4 of 64
Embedded System
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