IS46LR16320B-6BLA2 datasheet, PDF

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IS46LR16320B-6BLA2: Description32MX16 DDR DRAM, 5.5ns, PBGA60, 8 X 10 MM, LEAD FREE, MO-207, TFBGA-60; Categorystorage storage; File Size1MB，42 Pages; ManufacturerABLIC

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IS46LR16320B-6BLA2 Overview

32MX16 DDR DRAM, 5.5ns, PBGA60, 8 X 10 MM, LEAD FREE, MO-207, TFBGA-60

IS46LR16320B-6BLA2 Parametric

Parameter Name	Attribute value
Maker	ABLIC
Parts packaging code	DSBGA
package instruction	TFBGA,
Contacts	60
Reach Compliance Code	unknown
access mode	FOUR BANK PAGE BURST
Maximum access time	5.5 ns
Other features	AUTO/SELF REFRESH
JESD-30 code	R-PBGA-B60
length	10 mm
memory density	536870912 bit
Memory IC Type	DDR DRAM
memory width	16
Number of functions	1
Number of ports	1
Number of terminals	60
word count	33554432 words
character code	32000000
Operating mode	SYNCHRONOUS
Maximum operating temperature	105 °C
Minimum operating temperature	-40 °C
organize	32MX16
Package body material	PLASTIC/EPOXY
encapsulated code	TFBGA
Package shape	RECTANGULAR
Package form	GRID ARRAY, THIN PROFILE, FINE PITCH
Certification status	Not Qualified
Maximum seat height	1.1 mm
Maximum supply voltage (Vsup)	1.95 V
Minimum supply voltage (Vsup)	1.7 V
Nominal supply voltage (Vsup)	1.8 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal form	BALL
Terminal pitch	0.8 mm
Terminal location	BOTTOM
width	8 mm

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IS43LR16320B, IS46LR16320B

Advanced Information

16Bits

4Banks Mobile DDR SDRAM

Description

The IS43/46LR16320B is a 536,870,912 bits CMOS Mobile Double Data Rate Synchronous DRAM organized as 4 banks of 8,388,608 words x

16 bits. This product uses a double-data-rate architecture to achieve high-speed operation. The Data Input/ Output signals are transmitted

on a 16bit bus. The double data rate architecture is essentially a 2

prefetch architecture with an interface designed to transfer two data

words per clock cycle at the I/O pins. This product offers fully synchronous operations referenced to both rising and falling edges of the clock.

The data paths are internally pipelined and 2n-bits prefetched to achieve very high bandwidth. All input and output voltage levels are

compatible with LVCMOS.

Features

• JEDEC standard 1.8V power supply.

• VDD = 1.8V, VDDQ = 1.8V

• Four internal banks for concurrent operation

• MRS cycle with address key programs

- CAS latency 2, 3 (clock)

- Burst length (2, 4, 8, 16)

- Burst type (sequential & interleave)

• Fully differential clock inputs (CK, /CK)

• All inputs except data & DM are sampled at the rising

edge of the system clock

• Data I/O transaction on both edges of data strobe

• Bidirectional data strobe per byte of data (DQS)

• DM for write masking only

• Edge aligned data & data strobe output

• Center aligned data & data strobe input

• 64ms refresh period (8K cycle)

• Auto & self refresh

• Concurrent Auto Precharge

• Maximum clock frequency up to 166MHZ

• Maximum data rate up to 333Mbps/pin

• Special Power Saving supports.

- PASR (Partial Array Self Refresh)

- Auto TCSR (Temperature Compensated Self Refresh)

- Deep Power Down Mode

- Programmable Driver Strength Control by Full Strength

or 1/2, 1/4, 1/8 of Full Strength

• LVCMOS compatible inputs/outputs

• 60-Ball FBGA package

products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services

described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information

and before placing orders for products.

Rev.00A | February 2010

www.issi.com

- dram@issi.com

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Parts packaging code	DSBGA	DSBGA	DSBGA	DSBGA	DSBGA	DSBGA	DSBGA	DSBGA
package instruction	TFBGA,	TFBGA,	TFBGA,	TFBGA,	TFBGA,	TFBGA,	TFBGA,	TFBGA,
Contacts	60	60	60	60	60	60	60	60
Reach Compliance Code	unknown	unknown	unknown	unknown	unknown	unknown	unknown	unknown
access mode	FOUR BANK PAGE BURST	FOUR BANK PAGE BURST	FOUR BANK PAGE BURST	FOUR BANK PAGE BURST	FOUR BANK PAGE BURST	FOUR BANK PAGE BURST	FOUR BANK PAGE BURST	FOUR BANK PAGE BURST
Maximum access time	5.5 ns	5.5 ns	6 ns	5.5 ns	6 ns	5.5 ns	6 ns	6 ns
Other features	AUTO/SELF REFRESH	AUTO/SELF REFRESH	AUTO/SELF REFRESH	AUTO/SELF REFRESH	AUTO/SELF REFRESH	AUTO/SELF REFRESH	AUTO/SELF REFRESH	AUTO/SELF REFRESH
JESD-30 code	R-PBGA-B60	R-PBGA-B60	R-PBGA-B60	R-PBGA-B60	R-PBGA-B60	R-PBGA-B60	R-PBGA-B60	R-PBGA-B60
length	10 mm	10 mm	10 mm	10 mm	10 mm	10 mm	10 mm	10 mm
memory density	536870912 bit	536870912 bit	536870912 bit	536870912 bit	536870912 bit	536870912 bit	536870912 bit	536870912 bit
Memory IC Type	DDR DRAM	DDR DRAM	DDR DRAM	DDR DRAM	DDR DRAM	DDR DRAM	DDR DRAM	DDR DRAM
memory width	16	16	16	16	16	16	16	16
Number of functions	1	1	1	1	1	1	1	1
Number of ports	1	1	1	1	1	1	1	1
Number of terminals	60	60	60	60	60	60	60	60
word count	33554432 words	33554432 words	33554432 words	33554432 words	33554432 words	33554432 words	33554432 words	33554432 words
character code	32000000	32000000	32000000	32000000	32000000	32000000	32000000	32000000
Operating mode	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS
Maximum operating temperature	105 °C	85 °C	105 °C	70 °C	85 °C	85 °C	85 °C	70 °C
Minimum operating temperature	-40 °C	-40 °C	-40 °C	-	-40 °C	-40 °C	-40 °C	-
organize	32MX16	32MX16	32MX16	32MX16	32MX16	32MX16	32MX16	32MX16
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	TFBGA	TFBGA	TFBGA	TFBGA	TFBGA	TFBGA	TFBGA	TFBGA
Package shape	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
Package form	GRID ARRAY, THIN PROFILE, FINE PITCH	GRID ARRAY, THIN PROFILE, FINE PITCH	GRID ARRAY, THIN PROFILE, FINE PITCH	GRID ARRAY, THIN PROFILE, FINE PITCH	GRID ARRAY, THIN PROFILE, FINE PITCH	GRID ARRAY, THIN PROFILE, FINE PITCH	GRID ARRAY, THIN PROFILE, FINE PITCH	GRID ARRAY, THIN PROFILE, FINE PITCH
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
Maximum seat height	1.1 mm	1.1 mm	1.1 mm	1.1 mm	1.1 mm	1.1 mm	1.1 mm	1.1 mm
Maximum supply voltage (Vsup)	1.95 V	1.95 V	1.95 V	1.95 V	1.95 V	1.95 V	1.95 V	1.95 V
Minimum supply voltage (Vsup)	1.7 V	1.7 V	1.7 V	1.7 V	1.7 V	1.7 V	1.7 V	1.7 V
Nominal supply voltage (Vsup)	1.8 V	1.8 V	1.8 V	1.8 V	1.8 V	1.8 V	1.8 V	1.8 V
surface mount	YES	YES	YES	YES	YES	YES	YES	YES
technology	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS
Temperature level	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	COMMERCIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	COMMERCIAL
Terminal form	BALL	BALL	BALL	BALL	BALL	BALL	BALL	BALL
Terminal pitch	0.8 mm	0.8 mm	0.8 mm	0.8 mm	0.8 mm	0.8 mm	0.8 mm	0.8 mm
Terminal location	BOTTOM	BOTTOM	BOTTOM	BOTTOM	BOTTOM	BOTTOM	BOTTOM	BOTTOM
width	8 mm	8 mm	8 mm	8 mm	8 mm	8 mm	8 mm	8 mm
Maker	ABLIC	ABLIC	ABLIC	-	-	ABLIC	ABLIC	ABLIC

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