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DM74LS166 8-Bit Parallel-In/Serial-Out Shift Register
August 1986
Revised March 2000
DM74LS166
8-Bit Parallel-In/Serial-Out Shift Register
General Description
These parallel-in or serial-in, serial-out shift registers fea-
ture gated clock inputs and an overriding clear input. All
inputs are buffered to lower the drive requirements to one
normalized load, and input clamping diodes minimize
switching transients to simplify system design. The load
mode is established by the shift/load input. When HIGH,
this input enables the serial data input and couples the
eight flip-flops for serial shifting with each clock pulse.
When LOW, the parallel (broadside) data inputs are
enabled and synchronous loading occurs on the next clock
pulse. During parallel loading, serial data flow is inhibited.
Clocking is accomplished on the LOW-to-HIGH level edge
of the clock pulse through a two-input NOR gate, permitting
one input to be used as a clock-enable or clock-inhibit func-
tion. Holding either of the clock inputs HIGH inhibits clock-
ing; holding either LOW enables the other clock input. This
allows the system clock to be free running, and the register
can be stopped on command with the other clock input.
The clock-inhibit input should be changed to the high level
only while the clock input is HIGH. A buffered, direct clear
input overrides all other inputs, including the clock, and
sets all flip-flops to zero.
Ordering Code:
Order Number
DM74LS166M
DM74LS166WM
DM74LS166N
Package Number
M16A
M16B
N16E
Package Description
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
16-Lead Small Outline Intergrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
© 2000 Fairchild Semiconductor Corporation
DS006400
www.fairchildsemi.com
DM74LS166
Function Table
Inputs
Clear
Shift/
Load
L
H
H
H
H
H
X
X
L
H
H
X
Clock
Inhibit
X
L
L
L
L
H
X
L
↑
↑
↑
↑
X
X
X
H
L
X
Clock
Serial
Parallel
A…H
X
X
a…h
X
X
X
Internal
Outputs
Q
A
L
Q
A0
a
H
L
Q
A0
Q
B
L
Q
B0
b
Q
An
Q
An
Q
B0
L
Q
H0
h
Q
Gn
Q
Gn
Q
H0
Output
Q
H
H
=
HIGH Level (steady state)
L
=
LOW Level (steady state)
X
=
Don’t Care (any input, including transitions)
↑ =
Transition from LOW-to-HIGH level
a…h
=
The level of steady-state input at inputs A through H, respectively
Q
A0
, Q
B0
, Q
H0
=
The level of Q
A
, Q
B
, Q
H
, respectively, before the indicated steady-state input conditions were established
Q
An
, Q
Gn
,
=
The level of Q
A
, Q
G
, respectively, before the most recent
↑
transition of the clock
Logic Diagram
Timing Diagram
Typical Clear, Shift, Load, Inhibit and Shift Sequences
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2
DM74LS166
Absolute Maximum Ratings
(Note 1)
Supply Voltage
Input Voltage
Operating Free Air Temperature Range
Storage Temperature Range
7V
7V
0°C to
+70°C
−65°C
to
+150°C
Note 1:
The “Absolute Maximum Ratings” are those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the absolute maximum ratings.
The “Recommended Operating Conditions” table will define the conditions
for actual device operation.
Recommended Operating Conditions
Symbol
V
CC
V
IH
V
IL
I
OH
I
OL
f
CLK
t
W
t
SU
t
H
T
A
Supply Voltage
HIGH Level Input Voltage
LOW Level Input Voltage
HIGH Level Output Current
LOW Level Output Current
Clock Frequency (Note 2)
Clock Frequency (Note 3)
Pulse Width (Note 4)
Setup Time (Note 4)
Hold Time (Note 4)
Free Air Operating Temperature
Clock
Clear
Mode
Data
0
0
20
20
30
20
0
0
70
Parameter
Min
4.75
2
0.8
−0.4
8
25
20
Nom
5
Max
5.25
Units
V
V
V
mA
mA
MHz
MHz
ns
ns
ns
°C
Note 2:
C
L
=
15 pF, R
L
=
2 kΩ, T
A
=
25°C and V
CC
=
5V.
Note 3:
C
L
=
50 pF, R
L
=
2 kΩ, T
A
=
25°C and V
CC
=
5V.
Note 4:
T
A
=
25°C and V
CC
=
5V.
Electrical Characteristics
over recommended operating free air temperature range (unless otherwise noted)
Symbol
V
I
V
OH
V
OL
Parameter
Input Clamp Voltage
HIGH Level
Output Voltage
LOW Level
Output Voltage
I
I
I
IH
I
IL
I
OS
I
CC
Input Current @ Max Input Voltage
HIGH Level Input Current
LOW Level Input Current
Short Circuit Output Current
Supply Current
Conditions
V
CC
=
Min, I
I
= −18
mA
V
CC
=
Min, I
OH
=
Max
V
IL
=
Max, V
IH
=
Min
V
CC
=
Min, I
OL
=
Max
V
IL
=
Max, V
IH
=
Min
I
OL
=
4 mA, V
CC
=
Min
V
CC
=
Max, V
I
=
7V
V
CC
=
Max, V
I
=
2.7V
V
CC
=
Max, V
I
=
0.4V
V
CC
=
Max (Note 6)
V
CC
=
Max (Note 7)
−20
22
2.7
3.4
0.35
0.25
0.5
0.4
0.1
20
−0.4
−100
38
mA
µA
mA
mA
mA
Min
Typ
(Note 5)
Max
−1.5
Units
V
V
V
Note 5:
All typicals are at V
CC
=
5V, T
A
=
25°C.
Note 6:
Not more than one output should be shorted at a time, and the duration should not exceed one second.
Note 7:
With all outputs OPEN, 4.5V applied to the serial input, all other inputs except the CLOCK grounded, I
CC
is measured after a momentary ground,
then 4.5V is applied to the CLOCK.
3
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DM74LS166
Switching Characteristics
at V
CC
=
5V and T
A
=
25°C
From (Input)
Symbol
Parameter
To (Output)
C
L
=
15 pF
Min
f
MAX
t
PLH
t
PHL
t
PHL
Maximum Clock Frequency
Propagation Delay Time
LOW-to-HIGH Level Output
Propagation Delay Time
HIGH-to-LOW Level Output
Propagation Delay Time
HIGH-to-LOW Level Output
Clock to Output
Clock to Output
Clear to Output
25
8
8
6
35
35
30
Max
R
L
=
2 kΩ
C
L
=
50 pF
Min
20
38
41
36
Max
MHz
ns
ns
ns
Units
Parameter Measurement Information
Voltage Waveforms
Test Table for Synchronous Inputs
Data Input
for Test
H
Serial Input
0V
4.5V
Shift/Load
Output Tested
(See Note C)
Q
H
at T
N+1
Q
H
at T
N+8
Note A:
The clock pulse has the following characteristics: t
W(clock)
≥
20 ns and PRR
=
1 MHz. The clear pulse has the following characteristics:
t
W(clear)
≥
20 ns and t
HOLD
=
0 ns. When testing f
MAX
, vary the clock PRR.
Note B:
A clear pulse is applied prior to each test.
Note C:
Propagation delay times (t
PLH
and t
PHL
) are measured at t
n+1
. Proper shifting of data is verified at t
n+8
with a functional test.
Note D:
t
n
=
bit time before clocking transition
t
n+1
=
bit time after one clocking transition
t
n+8
=
bit time after eight clocking transitions
Note E:
V
REF
=
1.3V.
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