NCP51145
DDR 1.8 Amp Source / Sink
V
TT
Termination Regulator
The NCP51145 is a linear regulator designed to supply a regulated
V
TT
termination voltage for DDR−II, DDR−III, LPDDR−III and
DDR−IV memory applications. The regulator is capable of actively
sourcing and sinking
±
1.8 A peak currents while regulating an output
voltage to within
±
20 mV. The output termination voltage is regulated
to track V
DDQ
/ 2 by two external voltage divider resistors connected
to the PV
CC
, GND, and V
REF
pins.
The NCP51145 incorporates a high−speed differential amplifier to
provide ultra−fast response to line and load transients. Other features
include source/sink current limiting, soft−start and on−chip thermal
shutdown protection.
Features
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MARKING
DIAGRAMS
8
8
1
SOIC−8 EP
D SUFFIX
CASE 751BU
1
DFN8
MN SUFFIX
CASE 506AA
1
51145
AYWWG
G
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
For DDR V
TT
Applications, Source/Sink Currents:
Supports DDR−II to
±1.8
A, DDR−III to
±1.5
A
Supports LPDDR−III and DDR−IV to
±1.2
A
Stable Using Ceramic−Only (Very Low ESR) Capacitors
Integrated Power MOSFETs
High Accuracy V
TT
Output at Full−Load
Fast Transient Response
Built−in Soft−Start
Shutdown for Standby or Suspend Mode
Integrated Thermal and Current−Limit Protection
V
TT
Remote Sense Available in the DFN8 2x2mm Package
These Devices are Pb−Free and are RoHS Compliant
1
XXMG
G
51145
XX
M
A
Y
WW
G
= Specific Device Code
= Specific Device Code
= Date Code
= Assembly Location
= Year
= Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
PIN CONNECTIONS
1
PVCC
GND
VREF
V
TT
1
8
PVCC
V
CC
NC
NC
V
TT
NC
V
TTS
NC
V
CC
VREF
GND
NC
SOIC−8 EP
DFN8 2x2, 0.5P
(Top Views)
8
Typical Applications
DDR−II / DR−III / DDR−IV SDRAM Termination Voltage
Motherboard, Notebook, and VGA Card Memory Termination
Set Top Box, Digital TV, Printers
Low Power DDR−3LP
ORDERING INFORMATION
Device
NCP51145PDR2G
NCP51145MNTAG
Package
SOIC−8
(Pb−Free)
DFN−8
(Pb−Free)
Shipping
†
2500 / Tape &
Reel
3000 / Tape &
Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
©
Semiconductor Components Industries, LLC, 2015
1
April, 2017 − Rev. 3
Publication Order Number:
NCP51145/D
NCP51145
NCP51145
SO8−EP Package
PV
CC
= 1.0 to 5.5 V*
C2
R2
100k
2
GND
1
R4
C3
2.2
5V
PV
CC
V
CC
6
3
V
REF
Enable
R1
100k
C1
C4
V
TT
4
V
TT
= 0.6 to 2.5 V*
R3
EP
C1 = 1 to 100 nF Ceramic
C2 = 10
mF
Ceramic
C3 = 1
mF
C4 = 10
mF
Ceramic
R3 = Optional V
TT
Discharge Resistor
N−Ch MOSFET = Optional Enable / Disable
*For DDR2: PV
CC
= 1.8 V, V
TT
= 0.9 V
DDR3: PV
CC
= 1.5 V, V
TT
= 0.75 V
DDR4: PV
CC
= 1.2 V, V
TT
= 0.60 V
Figure 1. Application Diagram
PIN FUNCTION DESCRIPTION
Pin No.
SO8−EP
1
2
3
Pin No.
DFN8
1
4
5
Pin Name
PV
CC
GND
V
REF
Description
Input voltage which supplies current to the output pin. C
IN
^
½
S
C
OUT
Common Ground
Buffered reference voltage input equal to
½
of V
DDQ
and active low shutdown pin. An
external resistor divider dividing down the PV
CC
voltage creates the regulated output
voltage. Pulling the pin to ground (0.15 V maximum) turns the device off.
Regulator output voltage capable of sourcing and sinking current while regulating the
output rail. C
OUT
= 10
mF
Ceramic, or greater
True No Connect
The V
CC
pin is a 5 V input pin that provides internal bias to the controller. PV
CC
should
always be kept lower or equal to V
CC
.
V
TT
Sense
Pad for thermal connection. The exposed pad must be connected to the ground plane
using multiple vias for maximum power dissipation performance.
4
5, 7, 8
6
−
EP
2
3, 7
8
6
EP
V
TT
NC
V
CC
V
TTS
EPAD
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2
NCP51145
ABSOLUTE MAXIMUM RATINGS
Rating
Input Supply Voltage Range (V
cc
w
PV
CC
) (Note 1)
Output Voltage Range
Reference Input Range
Maximum Junction Temperature
Storage Temperature Range
ESD Capability, Human Body Model (Note 2)
ESD Capability, Machine Model (Note 2)
Lead Temperature Soldering
Reflow (SMD Styles Only), Pb−Free Versions (Note 3)
Symbol
PV
CC
,
V
CC
V
TT
V
REF
T
J(max)
TSTG
ESDHBM
ESDMM
T
SLD
Value
−0.3 to 6
−0.3 to 6
−0.3 to 6
150
−65 to 150
2
200
260
Unit
V
V
V
°C
°C
kV
V
°C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Refer to ELECTRICAL CHARACTERISTICS and APPLICATION INFORMATION for Safe Operating Area.
2. This device series incorporates ESD protection and is tested by the following methods:
ESD Human Body Model tested per AEC−Q100−002 (EIA/JESD22−A114)
ESD Machine Model tested per AEC−Q100−003 (EIA/JESD22−A115)
Latchup Current Maximum Rating:
≤150
mA per JEDEC standard: JESD78
3. For information, please refer to our Soldering and Mounting Techniques Reference Manual, SOLDERRM/D
THERMAL CHARACTERISTICS
Rating
Thermal Characteristics, SO8−EP (Note 4)
Thermal Resistance, Junction−to−Air (Note 5)
Thermal Reference, Junction−to−Lead2 (Note 5)
Symbol
R
qJA
R
YJL
Value
82
TBD
Unit
°C/W
4. Refer to ELECTRICAL CHARACTERISTIS and APPLICATION INFORMATION for Safe Operating Area.
5. Values based on copper area of 645 mm
2
(or 1 in
2
) of 1 oz copper thickness and FR4 PCB substrate.
OPERATING RANGES
(Note 6)
Rating
Input Voltage
Bias Supply Voltage
Ambient Temperature
Symbol
PV
CC
V
CC
T
A
Min
1.0
4.75
−40
Max
5.5
5.25
85
Unit
V
V
°C
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
6. Refer to ELECTRICAL CHARACTERISTICS and APPLICATION INFORMATION for Safe Operating Area.
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3
NCP51145
ELECTRICAL CHARACTERISTICS
PV
CC
= 1.8 V / 1.5 V; V
CC
= 5 V; V
REF
= 0.9 V / 0.75 V; C
TT
= 10
mF
(Ceramic), T
A
= +25°C, unless otherwise specified.
Parameter
REGULATOR OUTPUT
Output Offset Voltage
Load Regulation
I
out
= 0 A
I
out
=
±1.8
A, PV
CC
= 1.8 V, V
REF
= 0.9 V
I
out
=
±1.5
A, PV
CC
= 1.5 V, V
REF
= 0.75 V
I
out
=
±1.2
A, PV
CC
= 1.35 V, V
REF
= 0.675 V
I
out
=
±1.2
A, PV
CC
= 1.2 V, V
REF
= 0.6 V
INPUT AND STANDBY CURRENTS
Bias Supply Current
Standby Current
CURRENT LIMIT PROTECTION
Current Limit
SHUTDOWN THRESHOLDS
Enable
Shutdown Threshold Voltage
THERMAL SHUTDOWN
Thermal Shutdown Temperature
Thermal Shutdown Hysteresis
V
CC
= 5 V
V
CC
= 5 V
T
SD
T
SH
−
−
125
35
−
−
°C
°C
Shutdown
V
IH
V
IL
0.45
−
−
−
−
0.15
V
PV
CC
= 1.8 V, V
REF
= 0.9 V
PV
CC
= 1.5 V, V
REF
= 0.75 V
2
I
LIM
1.5
−
−
3.5
3.5
A
I
out
= 0 A
V
REF
< 0.2 V (Shutdown), R
LOAD
= 180W
I
BIAS
I
STB
−
−
1
2
2.5
90
mA
mA
Reg
load
−4
−
+4
mV
V
OS
−16
−
+16
mV
Test Conditions
Symbol
Min
Typ
Max
Unit
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
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4
NCP51145
PACKAGE DIMENSIONS
SOIC8−NB EP
CASE 751BU
ISSUE E
D
8
A
5
NOTE 5
2X
F
NOTE 6
0.10 C D
A1
E
2X 4 TIPS
E1
NOTE 4
L2
L
DETAIL A
0.20 C
1
NOTE 5
C
4
8X
SEATING
PLANE
B
TOP VIEW
NOTE 4
b
0.25
2X
M
C A-B D
0.10 C A-B
8X
DETAIL A
0.10 C
D
h
0.10 C
A
B
B
END VIEW
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION SHALL
BE 0.10mm IN EXCESS OF MAXIMUM MATERIAL
CONDITION.
4. DIMENSION D DOES NOT INCLUDE MOLD FLASH,
PROTRUSIONS, OR GATE BURRS. MOLD FLASH,
PROTRUSIONS, OR GATE BURRS SHALL NOT
EXCEED 0.15mm PER SIDE. DIMENSION E DOES
NOT INCLUDE INTERLEAD FLASH OR
PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED 0.25mm PER
SIDE. DIMENSIONS D AND E ARE DETERMINED AT
DATUM F.
5. DIMENSIONS A AND B ARE TO BE DETERMINED
AT DATUM F.
6. A1 IS DEFINED AS THE VERTICAL DISTANCE
FROM THE SEATING PLANE TO THE LOWEST
POINT ON THE PACKAGE BODY.
7. TAB CONTOUR MAY VARY MINIMALLY TO INCLUDE
TOOLING FEATURES.
DIM
A
A1
b
b1
c
c1
D
E
E1
e
F
G
h
L
L2
MILLIMETERS
MIN
MAX
1.35
1.75
0.00
0.10
0.31
0.51
0.28
0.48
0.17
0.25
0.17
0.23
4.90 BSC
6.00 BSC
3.90 BSC
1.27 BSC
1.55
2.39
1.55
2.39
0.25
0.50
0.40
1.27
0.25 BSC
e
SIDE VIEW
F
G
C
NOTE 7
SEATING
PLANE
b
c c1
SECTION B−B
BOTTOM VIEW
RECOMMENDED
SOLDERING FOOTPRINT*
2.60
2.60
8X
1.52
1
8X
1.27
PITCH
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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5
ÉÉÉ
ÇÇÇ
ÉÉÉ
ÇÇÇ
ÇÇÇ
b1
7.00
0.76
DIMENSION: MILLIMETERS
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