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IDT101A474S2.7DF

Description
Standard SRAM, 1KX4, 2.7ns, CDIP24
Categorystorage    storage   
File Size88KB,7 Pages
ManufacturerIDT (Integrated Device Technology)
Download Datasheet Parametric View All

IDT101A474S2.7DF Overview

Standard SRAM, 1KX4, 2.7ns, CDIP24

IDT101A474S2.7DF Parametric

Parameter NameAttribute value
Is it lead-free?Contains lead
Is it Rohs certified?incompatible
MakerIDT (Integrated Device Technology)
package instructionDIP, DIP24,.4
Reach Compliance Codecompliant
Maximum access time2.7 ns
I/O typeSEPARATE
JESD-30 codeR-XDIP-T24
JESD-609 codee0
memory density4096 bit
Memory IC TypeSTANDARD SRAM
memory width4
Negative supply voltage rating-5.2 V
Number of terminals24
word count1024 words
character code1000
Operating modeASYNCHRONOUS
Maximum operating temperature70 °C
Minimum operating temperature
organize1KX4
Output characteristicsOPEN-EMITTER
Package body materialCERAMIC
encapsulated codeDIP
Encapsulate equivalent codeDIP24,.4
Package shapeRECTANGULAR
Package formIN-LINE
Parallel/SerialPARALLEL
Peak Reflow Temperature (Celsius)225
power supply-5.2 V
Certification statusNot Qualified
surface mountNO
Temperature levelCOMMERCIAL
Terminal surfaceTin/Lead (Sn/Pb)
Terminal formTHROUGH-HOLE
Terminal pitch2.54 mm
Terminal locationDUAL
Maximum time at peak reflow temperature30
®
HIGH-SPEED BiCMOS
ECL STATIC RAM
4K (1K x 4-BIT) SRAM
Integrated Device Technology, Inc.
PRELIMINARY
IDT10474, IDT10A474
IDT100474, IDT100A474
IDT101474, IDT101A474
FEATURES:
• 1024-words x 4-bit organization
• Address access time: 2.7/3/3.5/4/4.5/5/7/8/10/15 ns
• Low power dissipation: 1000mW (typ.)
• Guaranteed Output Hold time
• Fully compatible with ECL logic levels
• Separate data input and output
• Corner and Center power pin pinouts
• Standard through-hole and surface mount packages
• Guaranteed-performance die available for MCMs/hybrids
• MIL-STD-883, Class B product available
DESCRIPTION:
The IDT10474(10A474), IDT100474(100A474) and
IDT101474(101A474) are 4,096-bit high-speed BiCMOS ECL
static random access memories organized as 1Kx4, with
separate data inputs and outputs. All I/Os are fully compatible
with ECL levels.
These devices are part of a family of asynchronous four-
bit-wide ECL SRAMs. This device is available in both the
traditional corner-power pinout, and "revolutionary" center-
power pin configurations. Because they are manufactured in
BiCMOS technology, power dissipation is greatly reduced
over equivalent bipolar devices. Low power operation pro-
vides higher system reliability and makes possible the use of
the plastic SOJ package for high-density surface mount
assembly.
The fast access time and guaranteed Output Hold time
allow greater margin for system timing variation. DataIN setup
time specified with respect to the trailing edge of Write Pulse
eases write timing allowing balanced Read and Write cycle
times.
FUNCTIONAL BLOCK DIAGRAM
A
0
V
CC
DECODER
4,096-BIT
MEMORY
ARRAY
V
EE
A
9
D
0
D
1
D
2
D
3
SENSE AMPS
AND READ/WRITE
CONTROL
Q
0
Q
1
Q
2
Q
3
WE
CS
2760 drw 01
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGE
©1992
Integrated Device Technology, Inc.
OCTOBER 1992
DSC-8022/3
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