®
HIGH-SPEED BiCMOS
ECL STATIC RAM
16K (4K x 4-BIT) SRAM
Integrated Device Technology, Inc.
PRELIMINARY
IDT10484, IDT10A484
IDT100484, IDT100A484
IDT101484, IDT101A484
FEATURES:
• 4096-words x 4-bit organization
• Address access time: 4/4.5/5/7/8/10/15 ns
• Low power dissipation: 900mW (typ.)
• Guaranteed Output Hold time
• Fully compatible with ECL logic levels
• Separate data input and output
• Corner and Center power pin pinouts
• Standard through-hole and surface mount packages
• Guaranteed-performance die available for MCMs/hybrids
• MIL-STD-883, Class B product available
DESCRIPTION:
The IDT10484(10A484), IDT100484(100A484) and
IDT101484(101A484) are 16,384-bit high-speed BiCEMOS™
ECL static random access memories organized as 4Kx4, with
separate data inputs and outputs. All I/Os are fully compatible
with ECL levels.
These devices are part of a family of asynchronous four-
bit-wide ECL SRAMs. This device is available in both the
traditional corner-power pinout, and "revolutionary" center-
power pin configurations. Because they are manufactured in
BiCEMOS™ technology, power dissipation is greatly reduced
over equivalent bipolar devices. Low power operation pro-
vides higher system reliability and makes possible the use of
the plastic SOJ package for high-density surface mount
assembly.
The fast access time and guaranteed Output Hold time
allow greater margin for system timing variation. DataIN setup
time specified with respect to the trailing edge of Write Pulse
eases write timing allowing balanced Read and Write cycle
times.
FUNCTIONAL BLOCK DIAGRAM
A
0
16,384-BIT
MEMORY ARRAY
DECODER
V
CC
V
EE
A
11
D
0
D
1
D
2
D
3
WE1
WE2
CS
SENSE AMPS
AND READ/WRITE
CONTROL
Q
0
Q
1
Q
2
Q
3
2811 drw 01
BiCEMOS is a trademark of Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGE
©1991
Integrated Device Technology, Inc.
JANUARY 1992
DSC-8018/4
1
IDT10484, IDT100484, IDT101484, IDT10A484, IDT100A484, IDT101A484
HIGH-SPEED BiCMOS ECL STATIC RAM 16K (4K x 4-BIT) SRAM
COMMERCIAL TEMPERATURE RANGE
PIN CONFIGURATIONS
D
0
D
1
D
2
D
3
Q
0
Q
1
V
CC
V
CCA
Q
2
Q
3
A
0
A
1
A
2
A
3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
CS VCC
A
Q
2
WE
1
Q
3
WE
2
A
0
NC
A
1
A
11
A
2
A
10
A
3
A
9
A
4
V
EE
A
5
NC
A
6
A
8
A
7
A
7
A
8
A
6
NC
A
5
V
EE
A
4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V
CC
Q
1
Q
0
D
3
D
2
D
1
D
0
CS
WE
1
WE
2
NC
A
11
A
10
A
9
PACKAGES
400-Mil-Wide
CERAMIC PACKAGE
C28-2
2811 drw 03
CENTER POWER
"A"
TOP VIEW
2811 drw 02a
CORNER POWER
"NON-A"
TOP VIEW
2811 drw 02b
400-Mil-Wide
CERPACK
E28-2
2811 drw 04a
300-Mil-Wide
PLASTIC SOJ PACKAGE
S028-5
2811 drw 04b
PIN DESCRIPTIONS
Symbol
A
0
through A
11
D
0
through D
3
Q
0
through Q
3
WE
1
, WE
2
CS
V
EE
V
CC
Pin Name
Address Inputs
Data Inputs
Data Outputs
Write Enable Inputs
Chip Select Input (Internal pull down)
More Negative Supply Voltage
Less Negative Supply Voltage
2811 tbl 01
Characterized Die
For Hybrid and MCM
Applications
2760 drw 05
LOGIC SYMBOL
CAPACITANCE
(T
A
= +25°C, f = 1.0MHz)
DIP
Symbol
C
IN
C
OUT
Parameter
Input
Capacitance
Output
Capacitance
Typ.
4
6
Max.
—
—
SOJ
Typ.
3
3
Max.
—
—
Unit
pF
pF
2811 tbl 02
D
0
D
1
D
2
D
3
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
Q
0
Q
1
Q
2
Q
3
TRUTH TABLE
(1)
CS
H
L
L
WE
1
, WE
2
X
*H
(2)
*L
(3)
DataOUT
L
RAM Data
L
Function
Deselected
Read
Write
2811 tbl 03
A
9
A
10
A
11
CS
WE
1
WE
2
2811 drw 06
NOTES:
1. H=High, L=Low, X=Don’t Care
2. *H = Either WE1 or WE2 are high.
3. *L = Both WE1 and WE2 are low.
2
IDT10484, IDT100484, IDT101484, IDT10A484, IDT100A484, IDT101A484
HIGH-SPEED BiCMOS ECL STATIC RAM 16K (4K x 4-BIT) SRAM
COMMERCIAL TEMPERATURE RANGE
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
V
TERM
T
A
Rating
Terminal Voltage
With Respect to GND
Operating
Temperature
10K
100K
101K
Ceramic
Plastic
Value
+0.5 to -7.0
0 to +75
0 to +85
0 to +75
-55 to +125
-65 to +150
-55 to +125
1.5
-50
Unit
V
°C
AC/DC ELECTRICAL OPERATING RANGES
I/O
10K
100K
V
EE
-5.2V
±
5%
-4.5V
±
5%
T
A
0 to +75°C, air flow exceeding 2 m/sec
0 to +85°C, air flow exceeding 2 m/sec
2760 tbl 05
101K -4.75V to -5.46V 0 to +75°C, air flow exceeding 2 m/sec
T
BIAS
T
STG
P
T
I
OUT
Temperature Under Bias
Storage
Temperatuure
°C
°C
W
mA
Power Dissipation
DC Output Current
(Output High)
NOTE:
2760 tbl 04
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS
may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions for ex-
tended periods may affect reliability.
DC ELECTRICAL CHARACTERISTICS
(1)
10K
Symbol
V
OH
Parameter
Output HIGH Voltage
(V
IN
= V
IH(Max)
or V
IL(Min)
)
Output LOW Voltage
(V
IN
= V
IH(Max)
or V
IL(Min)
)
Output Threshold HIGH Voltage
(V
IN
= V
IH(Min)
or V
IL(Max)
)
Output Threshold LOW Voltage
(V
IN
= V
IH(Min)
or V
IL(Max)
)
Input HIGH Voltage
(Guaranteed Input Voltage
High for All Inputs)
Input LOW Voltage
(Guaranteed Input Voltage
Low for All Inputs)
Input HIGH Current
CS
V
IN
= V
IH(Max)
Others
Input LOW Current
V
IN
= V
IL(Min)
CS
Others
Supply Current
Min.
-1000
-960
-900
-1870
-1850
-1830
-1020
-980
-920
—
—
—
-1145
-1105
-1045
-1870
-1850
-1830
—
—
0.5
-50
-210
Max.
-840
-810
-720
-1665
-1650
-1625
—
—
—
-1645
-1630
-1605
-840
-810
-720
-1490
-1475
-1450
220
110
170
90
—
TA
0°C
25°C
75°C
0°C
25°C
75°C
0°C
25°C
75°C
0°C
25°C
75°C
0°C
25°C
75°C
0°C
25°C
75°C
—
—
—
—
—
100K/101K
Min.
-1025
Max.
-880
Unit
mV
V
OL
-1810
-1620
mV
V
OHC
-1035
—
mV
V
OLC
—
-1610
mV
V
IH
-1165
-880
mV
V
IL
-1810
-1475
mV
I
IH
—
—
0.5
50
-190 (100K)
-210 (101K)
220
110
170
90
—
—
µA
µA
µA
µA
mA
I
IL
I
EE
NOTE:
1. RL = 50Ω to -2V, air flow exceeding 2 m/sec.
2760 tbl 05
3
IDT10484, IDT100484, IDT101484, IDT10A484, IDT100A484, IDT101A484
HIGH-SPEED BiCMOS ECL STATIC RAM 16K (4K x 4-BIT) SRAM
COMMERCIAL TEMPERATURE RANGE
AC TEST LOAD CONDITION
V
CC
(GND)
AC TEST INPUT PULSE
DATA
OUT
-0.9V
-1.7V
80%
20%
50Ω
30pF*
t
R
t
R
= t
F
= 2.0ns typ.
0.01µF
V
EE
-2.0V
*Includes probe and
jig capacitance
2811 drw 07
t
F
Note: All timing measurements are
referenced to 50% input levels.
2811 drw 08
RISE/FALL TIME
Symbol
tR
tF
Parameter
Output Rise Time
Output Fall Time
Min.
—
—
Typ.
2
2
Max.
—
—
Unit
ns
ns
2811 tbl 06
FUNCTIONAL DESCRIPTION
The IDT10484(10A484), IDT100484(100A484), and
IDT101484(101A484) BiCEMOS ECL static RAMs provide
high speed with low power dissipation typical of BiCMOS ECL.
These devices are available in both the traditional corner-
power pinout and the "revolutionary" center-power pinout for
reduced noise and improved system performance.
WRITE TIMING
To write data to the device, a Write Pulse need be formed
on the Write Enable input (WE) to control the write to the
SRAM array. This Write Pulse, called WE, is formed as the
logical AND of the WE1 and WE2 inputs; that is, when WE1 and
WE2 both are driven low, WE goes low and the write cycle
begins.
While CS and ADDR must be set-up when WE goes low,
DataIN can settle after the falling edge of WE, giving the data
path extra margin. Data is written to the memory cell at the end
of the Write Pulse, and addresses and Chip Select must be
held after the rising edge of the Write Pulse to ensure satisfac-
tory completion of the cycle.
DataOUT is disabled (held low) during the Write Cycle. If
CS is held low (active) and addresses remain unchanged, the
Data OUT pins will output the written data after "Write Recovery
time" (t
WR
).
Because of the very short Write Pulse requirement, these
devices can be cycled as quickly for Writes as for Reads.
READ TIMING
The read timing on these asynchronous devices is straight-
forward. DataOUT is held low until the device is selected by
Chip Select (CS). The Address (ADDR) settles and data
appears on the output after time t
AA
. Note that DataOUT is
held for a short time (t
OH
) after the address begins to change
for the next access, then ambiguous data is on the bus until a
new time t
AA
.
4
IDT10484, IDT100484, IDT101484, IDT10A484, IDT100A484, IDT101A484
HIGH-SPEED BiCMOS ECL STATIC RAM 16K (4K x 4-BIT) SRAM
COMMERCIAL TEMPERATURE RANGE
AC ELECTRICAL CHARACTERISTICS
(Over the AC Operating Range)
S4
Symbol
t
ACS
t
RCS
t
AA
t
OH
Parameter
(1)
Chip Select Access Time
Chip Select Recovery Time
Address Access Time
Data Hold from Address
Change
Read Cycle
—
—
—
1.0
2.5
2.5
4.0
—
—
—
—
1.0
2.5
2.5
4.5
—
—
—
—
1.0
3.0
3.0
5.0
—
—
—
—
1.0
3.5
3.5
7.0
—
—
—
—
1.0
5.0
5.0
8.0
—
—
—
—
1.0
5.0
5.0
10.0
—
—
—
—
1.0
5.0
5.0
15.0
—
ns
ns
ns
ns
2811 tbl 07
S4.5
S5
S7
S8
S10
S15
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit
NOTE:
1. Input and Output reference level is 50% point of waveform.
READ CYCLE GATED BY CHIP SELECT
(1, 2)
CS
t
ACS
DATA
OUT
2811 drw 09
t
RCS
READ CYCLE GATED BY ADDRESS
(1, 3)
ADDR
t
AA
t
OH
DATA
OUT
2811 drw 10
NOTES:
1. WE is high for read cycle.
2. Address valid prior to or minimum tAA-tACS before CS active.
3. CS active prior to or minimum tAA-tACS after address valid.
5
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