IS61NVP51236-200TQI datasheet, PDF

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IS61NVP51236-200TQI: Description512KX36 ZBT SRAM, 3.1ns, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, TQFP-100; Categorystorage storage; File Size244KB，35 Pages; ManufacturerIntegrated Silicon Solution ( ISSI )

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IS61NVP51236-200TQI Overview

512KX36 ZBT SRAM, 3.1ns, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, TQFP-100

IS61NVP51236-200TQI Parametric

Parameter Name	Attribute value
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Maker	Integrated Silicon Solution ( ISSI )
Parts packaging code	QFP
package instruction	14 X 20 MM, 1.40 MM HEIGHT, TQFP-100
Contacts	100
Reach Compliance Code	compliant
ECCN code	3A991.B.2.A
Factory Lead Time	12 weeks
Maximum access time	3.1 ns
Other features	PIPELINED ARCHITECTURE
Maximum clock frequency (fCLK)	200 MHz
I/O type	COMMON
JESD-30 code	R-PQFP-G100
JESD-609 code	e0
length	20 mm
memory density	18874368 bit
Memory IC Type	ZBT SRAM
memory width	36
Number of functions	1
Number of terminals	100
word count	524288 words
character code	512000
Operating mode	SYNCHRONOUS
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
organize	512KX36
Output characteristics	3-STATE
Package body material	PLASTIC/EPOXY
encapsulated code	LQFP
Encapsulate equivalent code	QFP100,.63X.87
Package shape	RECTANGULAR
Package form	FLATPACK, LOW PROFILE
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
power supply	2.5 V
Certification status	Not Qualified
Maximum seat height	1.6 mm
Maximum standby current	0.075 A
Minimum standby current	2.38 V
Maximum slew rate	0.475 mA
Maximum supply voltage (Vsup)	2.625 V
Minimum supply voltage (Vsup)	2.375 V
Nominal supply voltage (Vsup)	2.5 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	GULL WING
Terminal pitch	0.65 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	NOT SPECIFIED
width	14 mm

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IS61NLP25672/IS61NVP25672

IS61NLP51236/IS61NVP51236

IS61NLP102418/IS61NVP102418

256K x 72, 512K x 36 and 1M x 18

18Mb, PIPELINE 'NO WAIT' STATE

BUS SRAM

FEATURES

• 100 percent bus utilization

• No wait cycles between Read and Write

• Internal self-timed write cycle

• Individual Byte Write Control

• Single R/W (Read/Write) control pin

• Clock controlled, registered address,

data and control

• Interleaved or linear burst sequence control using

MODE input

• Three chip enables for simple depth expansion

and address pipelining

• Power Down mode

• Common data inputs and data outputs

•

CKE

pin to enable clock and suspend operation

• JEDEC 100-pin TQFP, 165-ball PBGA and 209-

ball (x72) PBGA packages

• Power supply:

NVP: V

2.5V (± 5%), V

DDQ

2.5V (± 5%)

NLP: V

3.3V (± 5%), V

DDQ

3.3V/2.5V (± 5%)

• JTAG Boundary Scan for PBGA packages

• Industrial temperature available

ISSI

FEBRUARY 2004

DESCRIPTION

The 18 Meg 'NLP/NVP' product family feature high-speed,

low-power synchronous static RAMs designed to provide

a burstable, high-performance, 'no wait' state, device for

networking and communications applications. They are

organized as 256K words by 72 bits, 512K words

by 36 bits and 1M words by 18 bits, fabricated with

ISSI

advanced CMOS technology.

Incorporating a 'no wait' state feature, wait cycles are

eliminated when the bus switches from read to write, or

write to read. This device integrates a 2-bit burst counter,

high-speed SRAM core, and high-drive capability outputs

into a single monolithic circuit.

All synchronous inputs pass through registers are controlled

by a positive-edge-triggered single clock input. Operations

may be suspended and all synchronous inputs ignored

when Clock Enable,

CKE

is HIGH. In this state the internal

device will hold their previous values.

All Read, Write and Deselect cycles are initiated by the

ADV input. When the ADV is HIGH the internal burst

counter is incremented. New external addresses can be

loaded when ADV is LOW.

Write cycles are internally self-timed and are initiated by

the rising edge of the clock inputs and when

is LOW.

Separate byte enables allow individual bytes to be written.

A burst mode pin (MODE) defines the order of the burst

sequence. When tied HIGH, the interleaved burst sequence

is selected. When tied LOW, the linear burst sequence is

selected.

FAST ACCESS TIME

Symbol

Parameter

Clock Access Time

Cycle Time

Frequency

-250

2.6

250

-200

3.1

200

Units

MHz

Copyright © 2004 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability

arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any

published information and before placing orders for products.

Integrated Silicon Solution, Inc. — www.issi.com —

1-800-379-4774

Rev. C

02/06/04

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