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IDT10A484S5DF

Description
Standard SRAM, 4KX4, 5ns, CDIP28
Categorystorage    storage   
File Size96KB,7 Pages
ManufacturerIDT (Integrated Device Technology)
Download Datasheet Parametric View All

IDT10A484S5DF Overview

Standard SRAM, 4KX4, 5ns, CDIP28

IDT10A484S5DF Parametric

Parameter NameAttribute value
Is it lead-free?Contains lead
Is it Rohs certified?incompatible
MakerIDT (Integrated Device Technology)
Reach Compliance Codenot_compliant
Maximum access time5 ns
I/O typeSEPARATE
JESD-30 codeR-XDIP-T28
JESD-609 codee0
memory density16384 bit
Memory IC TypeSTANDARD SRAM
memory width4
Negative supply voltage rating-5.2 V
Number of terminals28
word count4096 words
character code4000
Operating modeASYNCHRONOUS
Maximum operating temperature70 °C
Minimum operating temperature
organize4KX4
Output characteristicsOPEN-EMITTER
Package body materialCERAMIC
encapsulated codeDIP
Encapsulate equivalent codeDIP28,.4
Package shapeRECTANGULAR
Package formIN-LINE
Parallel/SerialPARALLEL
Peak Reflow Temperature (Celsius)225
power supply-5.2 V
Certification statusNot Qualified
surface mountNO
Temperature levelCOMMERCIAL
Terminal surfaceTin/Lead (Sn/Pb)
Terminal formTHROUGH-HOLE
Terminal pitch2.54 mm
Terminal locationDUAL
Maximum time at peak reflow temperature30
®
HIGH-SPEED BiCMOS
ECL STATIC RAM
16K (4K x 4-BIT) SRAM
Integrated Device Technology, Inc.
PRELIMINARY
IDT10484, IDT10A484
IDT100484, IDT100A484
IDT101484, IDT101A484
FEATURES:
• 4096-words x 4-bit organization
• Address access time: 4/4.5/5/7/8/10/15 ns
• Low power dissipation: 900mW (typ.)
• Guaranteed Output Hold time
• Fully compatible with ECL logic levels
• Separate data input and output
• Corner and Center power pin pinouts
• Standard through-hole and surface mount packages
• Guaranteed-performance die available for MCMs/hybrids
• MIL-STD-883, Class B product available
DESCRIPTION:
The IDT10484(10A484), IDT100484(100A484) and
IDT101484(101A484) are 16,384-bit high-speed BiCEMOS™
ECL static random access memories organized as 4Kx4, with
separate data inputs and outputs. All I/Os are fully compatible
with ECL levels.
These devices are part of a family of asynchronous four-
bit-wide ECL SRAMs. This device is available in both the
traditional corner-power pinout, and "revolutionary" center-
power pin configurations. Because they are manufactured in
BiCEMOS™ technology, power dissipation is greatly reduced
over equivalent bipolar devices. Low power operation pro-
vides higher system reliability and makes possible the use of
the plastic SOJ package for high-density surface mount
assembly.
The fast access time and guaranteed Output Hold time
allow greater margin for system timing variation. DataIN setup
time specified with respect to the trailing edge of Write Pulse
eases write timing allowing balanced Read and Write cycle
times.
FUNCTIONAL BLOCK DIAGRAM
A
0
16,384-BIT
MEMORY ARRAY
DECODER
V
CC
V
EE
A
11
D
0
D
1
D
2
D
3
WE1
WE2
CS
SENSE AMPS
AND READ/WRITE
CONTROL
Q
0
Q
1
Q
2
Q
3
2811 drw 01
BiCEMOS is a trademark of Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGE
©1991
Integrated Device Technology, Inc.
JANUARY 1992
DSC-8018/4
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