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Datasheet> All Categories > The embedded processor and controller> Microcontrollers and processors> IDT29FCT520BTQ
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IDT29FCT520BTQ

Description
Pipeline Register, 8-Bit, CMOS, PDSO24, QSOP-24
CategoryThe embedded processor and controller    Microcontrollers and processors   
File Size96KB，7 Pages
ManufacturerIDT (Integrated Device Technology)
Download Datasheet Parametric View All

IDT29FCT520BTQ Overview

Pipeline Register, 8-Bit, CMOS, PDSO24, QSOP-24

IDT29FCT520BTQ Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
MakerIDT (Integrated Device Technology)
Parts packaging codeSOIC
package instructionSOP, SSOP24,.24
Contacts24
Reach Compliance Codenot_compliant
Other featuresMULTIPLEXED OUTPUT
boundary scanNO
External data bus width8
JESD-30 codeR-PDSO-G24
JESD-609 codee0
length8.6868 mm
low power modeNO
Humidity sensitivity level1
Number of terminals24
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
Output data bus width8
Package body materialPLASTIC/EPOXY
encapsulated codeSOP
Encapsulate equivalent codeSSOP24,.24
Package shapeRECTANGULAR
Package formSMALL OUTLINE
Peak Reflow Temperature (Celsius)225
power supply5 V
Certification statusNot Qualified
Maximum seat height1.7272 mm
Maximum slew rate16.3 mA
Maximum supply voltage5.25 V
Minimum supply voltage4.75 V
Nominal supply voltage5 V
surface mountYES
technologyCMOS
Temperature levelINDUSTRIAL
Terminal surfaceTin/Lead (Sn85Pb15)
Terminal formGULL WING
Terminal pitch0.635 mm
Terminal locationDUAL
Maximum time at peak reflow temperature30
width3.937 mm
uPs/uCs/peripheral integrated circuit typeDSP PERIPHERAL, PIPELINE REGISTER

IDT29FCT520BTQ Preview

IDT29FCT520AT/BT/CT
MULTILEVEL PIPELINE REGISTER
INDUSTRIAL TEMPERATURE RANGE
MULTILEVEL
PIPELINE REGISTER
IDT29FCT520AT/BT/CT
FEATURES:
−
−
−
−
−
−
−
Low input and output leakage
≤1µ
A (max.)
CMOS power levels
True TTL input and output compatibility
•
V
OH
= 3.3V (typ.)
•
V
OL
= 0.3V (typ.)
High drive outputs (-15mA I
OH
, 48mA I
OL
)
Meets or exceeds JEDEC standard 18 specifications
A, B, and C speed grades
Available in SOIC, SSOP, and QSOP packages
DESCRIPTION:
The 29FCT520T contains four 8-bit positive edge-triggered registers.
These may be operated as a dual 2-level or as a single 4-level pipeline.
A single 8-bit input is provided and any of the four registers is available at
the 8-bit, 3-state output.
These devices are ideal for high speed burst writes and reads in
processor/memory applications.
FUNCTIONAL BLOCK DIAGRAM
D
0
- D
7
8
I
0
, I
1
2
M UX
REG ISTER
CONTRO L
CLK
1
OCTAL RE G. A1
OCTAL RE G. B1
OCTAL RE G. A2
OCTAL RE G. B2
2
S
0
, S
1
MUX
OE
8
Y
0
- Y
7
INDUSTRIAL TEMPERATURE RANGE
1
c
1999 Integrated Device Technology, Inc.
AUGUST 2000
DSC-4215/4
IDT29FCT520AT/BT/CT
MULTILEVEL PIPELINE REGISTER
INDUSTRIAL TEMPERATURE RANGE
PIN CONFIGURATION
I
0
I
1
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
CLK
GND
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
V
TERM(2)
Rating
Terminal Voltage with Respect to GND
Terminal Voltage with Respect to GND
Storage Temperature
DC Output Current
Max.
–0.5 to +7
–0.5 to V
CC
+0.5
–65 to +150
–60 to +120
Unit
V
V
°C
mA
8T-link
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
Vcc
S
0
S
1
Y
0
Y
1
Y
2
Y
3
Y
4
Y
5
Y
6
Y
7
OE
V
TERM(3)
T
STG
I
OUT
SO24-2
SO24-7
SO24-8
20
19
18
17
16
15
14
13
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or
any other conditions above those indicated in the operational sections
of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect reliability.
No
terminal voltage may exceed Vcc by +0.5V unless otherwise noted.
2. Inputs and Vcc terminals only.
3. Outputs and I/O terminals only.
CAPACITANCE
(T
A
= +25
O
C, f = 1.0MHz)
Symbol
C
IN
Parameter
(1)
Input Capacitance
Output Capacitance
Conditions
V
IN
= 0V
V
OUT
= 0V
Typ.
6
8
Max.
10
12
Unit
pF
pF
8T-link
SOIC/ SSOP/ QSOP
TOP VIEW
C
OUT
NOTE:
1. This parameter is measured at characterization but not tested.
PIN DESCRIPTION
Pin Names
Dn
CLK
I
0
, I
1
S
0
, S
1
OE
Yn
Description
Register Input Port
Clock Input. Enter data into registers on LOW-to-HIGH
transitions.
Instruction Inputs. See Figure 1 and Instruction Control
tables.
Multiplexer Select. Inputs either register A
1
, A
2
, B
1
, or B
2
data to be available at the Output Port.
Output Enable for 3-State Output Port
Register Output Port
REGISTER SELECTION
S
0
0
0
1
1
S
1
0
1
0
1
Register
B
2
B
1
A
2
A
1
2
IDT29FCT520AT/BT/CT
MULTILEVEL PIPELINE REGISTER
INDUSTRIAL TEMPERATURE RANGE
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Industrial: T
A
= -40°C to +85°C, V
CC
= 5.0V ± 5%
Symbol
V
IH
V
IL
I
IH
I
IL
I
OZH
I
OZL
I
I
V
IK
I
OS
V
OH
V
OL
V
H
I
CC
Input HIGH Current
(4)
Clamp Diode Voltage
Short Circuit Current
Output HIGH Voltage
Output LOW Voltage
Input Hysteresis
Quiescent Power Supply Current
V
CC
= Max., V
I
= V
CC
(Max.)
V
CC
= Min., I
IN
= –18mA
V
CC
= Max.
(3)
, V
O
= GND
V
CC
= Min.
V
IN
= V
IH
or V
IL
V
CC
= Min.
V
IN
= V
IH
or V
IL
—
V
CC
= Max., V
IN
=
GND or
V
CC
I
OH
= –8mA
I
OH
= –15mA
I
OH
= 48mA
Parameter
Input HIGH Level
Input LOW Level
Input HIGH Current
(4)
Input LOW Current
(4)
High Impedance Output Current
(4)
V
CC
= Max.
Test Conditions
(1)
Guaranteed Logic HIGH Level
Guaranteed Logic LOW Level
V
CC
= Max.
V
I
= 2.7V
V
I
= 0.5V
V
O
= 2.7V
V
O
= 0.5V
Min.
2
—
—
—
—
—
—
—
–60
2.4
2
—
—
—
Typ.
(2)
—
—
—
—
—
—
—
–0.7
–120
3.3
3
0.3
200
0.01
Max.
—
0.8
±1
±1
±1
±1
±1
–1.2
–225
—
—
0.5
—
1
V
mV
µA
µA
V
mA
V
µA
Unit
V
V
µA
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at V
CC
= 5.0V, +25°C ambient.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.
4. The test limit for this parameter is ±5µ A at T
A
= -55°C.
DUAL 2-LEVEL
SINGLE 4-LEVEL
A
1
B
1
A
1
B
1
A
1
B
1
A
2
B
2
A
2
B
2
A
2
B
2
I=2
NOTE:
1. I = 3 for hold.
I=1
I=0
Figure 1. Data Loading in 2-Level Operation
3
IDT29FCT520AT/BT/CT
MULTILEVEL PIPELINE REGISTER
INDUSTRIAL TEMPERATURE RANGE
POWER SUPPLY CHARACTERISTICS
Symbol
∆I
CC
I
CCD
Parameter
Quiescent Power Supply Current
TTL Inputs HIGH
Dynamic Power Supply Current
(4)
Test Conditions
(1)
V
CC
= Max.
V
IN
= 3.4V
(3)
V
CC
= Max., Outputs Open
OE
= GND
One Input Toggling
50% Duty Cycle
V
CC
= Max., Outputs Open
f
CP
= 10MHz
50% Duty Cycle
OE
= GND
One Bit Toggling
at fi = 5MHz
50% Duty Cycle
V
CC
= Max., Outputs Open
f
CP
= 10MHz
50% Duty Cycle
OE
= GND
Eight Bits Toggling
at fi = 2.5MHz
50% Duty Cycle
Min.
—
—
Typ.
(2)
0.5
0.15
Max.
2
0.25
Unit
mA
mA/
MHz
V
IN
= V
CC
V
IN
= GND
I
C
Total Power Supply Current
(6)
V
IN
= V
CC
V
IN
= GND
—
1.5
3.5
mA
V
IN
= 3.4V
V
IN
= GND
V
IN
= V
CC
V
IN
= GND
—
2
5.5
—
3.8
7.3
(5)
V
IN
= 3.4V
V
IN
= GND
—
6
16.3
(5)
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at V
CC
= 5.0V, +25°C ambient.
3. Per TTL driven input (V
IN
= 3.4V). All other inputs at V
CC
or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.
5. Values for these conditions are examples of the I
CC
formula. These limits are guaranteed but not tested.
6. I
C
= I
QUIESCENT
+ I
INPUTS
+ I
DYNAMIC
I
C
= I
CC
+
∆I
CC
D
H
N
T
+ I
CCD
(f
CP/
2 + f
i
N
i
)
I
CC
= Quiescent Current
∆I
CC
= Power Supply Current for a TTL High Input (V
IN
= 3.4V)
D
H
= Duty Cycle for TTL Inputs High
N
T
= Number of TTL Inputs at D
H
I
CCD
= Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
f
CP
= Clock Frequency for Register Devices (Zero for Non-Register Devices)
f
i
= Input Frequency
N
i
= Number of Inputs at f
i
All currents are in milliamps and all frequencies are in megahertz.
4
IDT29FCT520AT/BT/CT
MULTILEVEL PIPELINE REGISTER
INDUSTRIAL TEMPERATURE RANGE
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
FCT520AT
Symbol
t
PHL
t
PLH
t
PHL
t
PLH
t
SU
t
H
t
SU
t
H
t
PHZ
t
PLZ
t
PZH
t
PZL
t
W
Parameter
Propagation Delay
CLK to Yn
Propagation Delay
S
0
or S
1
to Yn
Set-up Time, HIGH or LOW
Dn to CLK
Hold Time, HIGH or LOW
Dn to CLK
Set-up Time, HIGH or LOW
I
0
or I
1
to CLK
Hold Time, HIGH or LOW
I
0
or I
1
to CLK
Output Disable Time
Output Enable Time
Clock Pulse Width, HIGH or LOW
Condition
(1)
C
L
= 50pF
R
L
= 500Ω
Min
.
(2)
2
2
5
2
5
2
1.5
1.5
7
Max
.
14
13
—
—
—
—
12
15
—
FCT520BT
Min
.
(2)
2
2
2.5
2
4
2
1.5
1.5
5.5
Max
.
7.5
7.5
—
—
—
—
7
7.5
—
FCT520CT
Min
.
(2)
2
2
2.5
2
4
2
1.5
1.5
5.5
Max
.
6
6
—
—
—
—
6
6
—
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
NOTES:
1. See Test Curcuits and Waveforms.
2. Minimum values are guaranteed but not tested on Propagation Delays.
5
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