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Datasheet> All Categories > logic> logic> IDT74FCT162841CTPV8
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IDT74FCT162841CTPV8

Description
Bus Driver, FCT Series, 2-Func, 10-Bit, True Output, CMOS, PDSO56, SSOP-56
Categorylogic    logic   
File Size60KB，7 Pages
ManufacturerIDT (Integrated Device Technology)
Download Datasheet Parametric View All

IDT74FCT162841CTPV8 Overview

Bus Driver, FCT Series, 2-Func, 10-Bit, True Output, CMOS, PDSO56, SSOP-56

IDT74FCT162841CTPV8 Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
MakerIDT (Integrated Device Technology)
Parts packaging codeSSOP
package instructionSSOP, SSOP56,.4
Contacts56
Reach Compliance Codenot_compliant
Other featuresMAX OUTPUT SKEW = 0.5NS; TYP VOLP < 0.6V @ VCC = 5V, TA = 25 DEGREE C
seriesFCT
JESD-30 codeR-PDSO-G56
JESD-609 codee0
length18.415 mm
Load capacitance (CL)50 pF
Logic integrated circuit typeBUS DRIVER
MaximumI(ol)0.024 A
Humidity sensitivity level1
Number of digits10
Number of functions2
Number of ports2
Number of terminals56
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
Output characteristics3-STATE WITH SERIES RESISTOR
Output polarityTRUE
Package body materialPLASTIC/EPOXY
encapsulated codeSSOP
Encapsulate equivalent codeSSOP56,.4
Package shapeRECTANGULAR
Package formSMALL OUTLINE, SHRINK PITCH
method of packingTAPE AND REEL
Peak Reflow Temperature (Celsius)225
power supply5 V
Prop。Delay @ Nom-Sup5.5 ns
propagation delay (tpd)7.5 ns
Certification statusNot Qualified
Maximum seat height2.794 mm
Maximum supply voltage (Vsup)5.5 V
Minimum supply voltage (Vsup)4.5 V
Nominal supply voltage (Vsup)5 V
surface mountYES
technologyCMOS
Temperature levelINDUSTRIAL
Terminal surfaceTin/Lead (Sn85Pb15)
Terminal formGULL WING
Terminal pitch0.635 mm
Terminal locationDUAL
Maximum time at peak reflow temperatureNOT SPECIFIED
width7.5 mm

IDT74FCT162841CTPV8 Preview

IDT74FCT162841AT/CT
FAST CMOS 20-BIT TRANSPARENT LATCH
INDUSTRIAL TEMPERATURE RANGE
FAST CMOS 20-BIT
TRANSPARENT LATCH
IDT74FCT162841AT/CT
FEATURES:
•
•
•
•
•
•
•
•
0.5 MICRON CMOS Technology
High-speed, low-power CMOS replacement for ABT functions
Typical t
SK(o)
(Output Skew) < 250ps
Low input and output leakage
≤
1µA (max.)
V
CC
= 5V ±10%
Balanced Output Drivers ±24mA
Reduced system switching noise
Typical V
OLP
(Output Ground Bounce) < 0.6V at V
CC
= 5V,
T
A
= 25°C
• Available in SSOP and TSSOP packages
DESCRIPTION:
The FCT162841T 20-bit transparent D-type latches are built using advanced
dual metal CMOS technology. These high-speed, low-power latches are ideal
for temporary data storage. They can be used for implementing memory address
latches, I/O ports, and bus drivers. The Output Enable (OE) and Latch Enable
(LE) controls are organized to operate each device as two 10-bit latches or one
20-bit latch. Flow-through organization of signal pins simplifies layout. All inputs
are designed with hysteresis for improved noise margin.
The FCT162841T has balanced output drive with current limiting resistors.
This offers low ground bounce, minimal undershoot, and controlled output fall
times–reducing the need for external series terminating resistors. The
FCT162841T is a plug-in replacement for the FCT16841T and ABT16841 for
on-board interface applications.
FUNCTIONAL BLOCK DIAGRAM
1
OE
1
2
OE
28
1
LE
56
2
LE
29
1
D
1
55
D
2
2
D
1
42
D
15
C
1
Q
1
C
2
Q
1
TO NINE OTH ER CH ANN ELS
TO N IN E OTHER CHANNELS
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE
1
© 2002 Integrated Device Technology, Inc.
JUNE 2002
DSC-5467/2
IDT74FCT162841AT/CT
FAST CMOS 20-BIT TRANSPARENT LATCH
INDUSTRIAL TEMPERATURE RANGE
PIN CONFIGURATION
1
OE
1
Q
1
1
Q
2
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
Description
Terminal Voltage with Respect to GND
Terminal Voltage with Respect to GND
Storage Temperature
DC Output Current
Max
–0.5 to 7
–0.5 to V
CC
+0.5
–65 to +150
–60 to +120
Unit
V
V
°C
mA
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
1
LE
1
D
1
1
D
2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
V
TERM(2)
V
TERM(3)
T
STG
I
OUT
GND
1
Q
3
1
Q
4
GND
1
D
3
1
D
4
V
CC
1
Q
5
1
Q
6
1
Q
7
V
CC
1
D
5
1
D
6
1
D
7
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
2. All device terminals except FCT162XXX Output and I/O terminals.
3. Outputs and I/O terminals for FCT162XXX.
GND
1
Q
8
1
Q
9
1
Q
10
2
Q
1
2
Q
2
2
Q
3
GND
1
D
8
1
D
9
1
D
10
2
D
1
2
D
2
2
D
3
CAPACITANCE
(T
A
= +25°C, f = 1.0MHz)
Symbol
C
IN
C
OUT
Parameter
(1)
Input Capacitance
Output Capacitance
Conditions
V
IN
= 0V
V
OUT
= 0V
Typ.
3.5
3.5
Max.
6
8
Unit
pF
pF
NOTE:
1. This parameter is measured at characterization but not tested.
GND
2
Q
4
2
Q
5
2
Q
6
GND
2
D
4
2
D
5
2
D
6
PIN DESCRIPTION
Pin Names
xDx
xLE
xOE
xQx
Data Inputs
Latch Enable Inputs (Active HIGH)
Output Enable Inputs (Active LOW)
3-State Outputs
Description
V
CC
2
Q
7
2
Q
8
V
CC
2
D
7
2
D
8
GND
2
Q
9
2
Q
10
2
OE
GND
2
D
9
2
D
10
2
LE
FUNCTION TABLE
(1)
xDx
H
L
X
X
Inputs
xLE
H
H
L
X
xOE
L
L
L
H
Outputs
xQx
H
L
Q
(2)
Z
SSOP/ TSSOP
TOP VIEW
NOTES:
1. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
Z = High-Impedance
2. Output level before xLE HIGH-to-LOW transition.
2
IDT74FCT162841AT/CT
FAST CMOS 20-BIT TRANSPARENT LATCH
INDUSTRIAL TEMPERATURE RANGE
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Industrial: T
A
= –40°C to +85°C, V
CC
= 5.0V ±10%
Symbol
V
IH
V
IL
I
IH
Parameter
Input HIGH Level
Input LOW Level
Input HIGH Current (Input pins)
(5)
Input HIGH Current (I/O pins)
(5)
I
IL
Input LOW Current (Input pins)
(5)
Input LOW Current (I/O pins)
(5)
I
OZH
I
OZL
V
IK
I
OS
V
H
I
CCL
I
CCH
I
CCZ
High Impedance Output Current
(3-State Output pins)
(5)
Clamp Diode Voltage
Short Circuit Current
Input Hysteresis
Quiescent Power Supply Current
V
CC
= Max.
V
IN
= GND or V
CC
V
CC
= Min., I
IN
= –18mA
V
CC
= Max., V
O
= GND
(3)
—
V
CC
= Max.
V
O
= 2.7V
V
O
= 0.5V
V
I
= GND
Test Conditions
(1)
Guaranteed Logic HIGH Level
Guaranteed Logic LOW Level
V
CC
= Max.
V
I
= V
CC
Min.
2
—
—
—
—
—
—
—
—
–80
—
—
Typ.
(2)
—
—
—
—
—
—
—
—
–0.7
–140
100
5
Max.
—
0.8
±1
±1
±1
±1
±1
±1
–1.2
–250
—
500
V
mA
mV
µA
µA
Unit
V
V
µA
OUTPUT DRIVE CHARACTERISTICS
Symbol
I
ODL
I
ODH
V
OH
V
OL
Parameter
Output LOW Current
Output HIGH Current
Output HIGH Voltage
Output LOW Voltage
Test Conditions
(1)
V
CC
= 5V
,
V
IN =
V
IH
or V
IL,
V
O
= 1.5V
(3)
V
CC
= 5V
,
V
IN =
V
IH
or V
IL,
V
O
= 1.5V
(3)
V
CC
= Min
I
OH
= –24mA
V
IN
= V
IH
or V
IL
V
CC
= Min
I
OH
= 24mA
V
IN
= V
IH
or V
IL
Min.
60
–60
2.4
—
Typ.
(2)
115
–115
3.3
0.3
Max.
200
–200
—
0.55
Unit
mA
mA
V
V
NOTES:
1. For conditions shown as Min. or Max., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at V
CC
= 5.0V, +25°C ambient.
3. Not more than one output should be tested at one time. Duration of the test should not exceed one second.
4. Duration of the condition can not exceed one second.
5. This test limit for this parameter is ±5µA at T
A
= –55°C.
3
IDT74FCT162841AT/CT
FAST CMOS 20-BIT TRANSPARENT LATCH
INDUSTRIAL TEMPERATURE RANGE
POWER SUPPLY CHARACTERISTICS
Symbol
∆I
CC
I
CCD
Parameter
Quiescent Power Supply Current
TTL Inputs HIGH
Dynamic Power Supply Current
(4)
Test Conditions
(1)
V
CC
= Max.
V
IN
= 3.4V
(3)
V
CC
= Max.
Outputs Open
xOE = GND
One Input Toggling
50% Duty Cycle
V
CC
= Max.
Outputs Open
fi = 10MHz
50% Duty Cycle
xOE = GND
xLE = V
CC
One Bit Toggling
V
CC
= Max.
Outputs Open
fi = 2.5MHz
50% Duty Cycle
xOE = GND
xLE = V
CC
Twenty Bits Toggling
V
IN
= V
CC
V
IN
= GND
Min.
—
—
Typ.
(2)
0.5
60
Max.
1.5
100
Unit
mA
µA/
MHz
I
C
Total Power Supply Current
(6)
V
IN
= V
CC
V
IN
= GND
V
IN
= 3.4V
V
IN
= GND
—
0.6
1.5
mA
—
0.9
2.3
V
IN
= V
CC
V
IN
= GND
V
IN
= 3.4V
V
IN
= GND
—
3
5.5
(5)
—
8
20.5
(5)
NOTES:
1. For conditions shown as Min. or Max., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at V
CC
= 5.0V, +25°C ambient.
3. Per TTL driven input (V
IN
= 3.4V). All other inputs at V
CC
or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.
5. Values for these conditions are examples of the I
CC
formula. These limits are guaranteed but not tested.
6. I
C
= I
QUIESCENT
+ I
INPUTS
+ I
DYNAMIC
I
C
= I
CC
+
∆I
CC
D
H
N
T
+ I
CCD
(f
CP
N
CP
/2 + fiNi)
I
CC
= Quiescent Current (I
CCL
, I
CCH
and I
CCZ
)
∆I
CC
= Power Supply Current for a TTL High Input (V
IN
= 3.4V)
D
H
= Duty Cycle for TTL Inputs High
N
T
= Number of TTL Inputs at D
H
I
CCD
= Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
f
CP
= Clock Frequency for Register Devices (Zero for Non-Register Devices)
N
CP
= Number of Clock Inputs at f
CP
f
i
= Input Frequency
N
i
= Number of Inputs at f
i
4
IDT74FCT162841AT/CT
FAST CMOS 20-BIT TRANSPARENT LATCH
INDUSTRIAL TEMPERATURE RANGE
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
FCT162841AT
Symbol
t
PLH
t
PHL
Parameter
Propagation Delay
xDx to xQx
(LE = HIGH)
Propagation Delay
xLE to xQx
Condition
(1)
C
L
= 50pF
R
L
= 500Ω
C
L
= 300pF
(5)
R
L
= 500Ω
C
L
= 50pF
R
L
= 500Ω
C
L
= 300pF
(5)
R
L
= 500Ω
C
L
= 50pF
R
L
= 500Ω
C
L
= 300pF
(5)
R
L
= 500Ω
C
L
= 5pF
(5)
R
L
= 500Ω
C
L
= 50pF
R
L
= 500Ω
C
L
= 50pF
R
L
= 500Ω
Min.
(2)
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
2.5
2.5
4
(4)
—
Max.
9
13
12
16
11.5
23
7
8
—
—
—
0.5
FCT162841CT
Min.
(2)
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1
1
3
(4)
—
Max.
3.8
7.5
3.8
7.5
4.6
9
3.6
3.6
—
—
—
0.5
ns
ns
ns
ns
ns
ns
ns
Unit
ns
t
PLH
t
PHL
t
PZH
t
PZL
Output Enable Time
xOE to xQx
t
PHZ
t
PLZ
Output Disable Time
xOE to xQx
t
SU
t
H
t
W
t
SK(o)
Set-Up Time
HIGH or LOW, xDx to xLE
Hold Time
HIGH or LOW, xDx to xLE
xLE Pulse, Width HIGH
Output Skew
(3)
NOTES:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design.
4. This limit is guaranteed but not tested.
5. This condition is guaranteed but not tested.
5
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