HY62V8200-(I)/HY62U8200-(I) Series
256Kx8bit CMOS SRAM
DESCRIPTION
The HY62V8200-(I)/HY62U8200-(I) is a high
speed, low power and 2M bit CMOS SRAM
organized as 262,144 words by 8bit. The
HY62V8200-(I) / HY62U8200-(I) uses high
performance CMOS process technology and
designed for high speed low power circuit
technology. It is particularly well suited for used in
high density low power system application. This
device has a data retention mode that guarantees
data to remain valid at a minimum power supply
voltage of 2.0V.
FEATURES
•
Fully static operation and Tri-state output
•
TTL compatible inputs and outputs
•
Battery backup( L/LL-part )
- 2.0V(min) data retention
•
Standard pin configuration
- 32pin 8x20mm TSOP-I / 8x13.4mm TSOP-I
(Standard and Reversed)
Product
Voltage
Speed
Operation
Standby Current(uA)
No.
(V)
(ns)
Current(mA)
L
LL
HY62V8200
3.3
70*/85/100
5
50
15
HY62V8200-I
3.3
70*/85/100
5
50
20
HY62U8200
3.0
70*/85/100
5
50
15
HY62U8200-I
3.0
70*/85/100
5
50
20
Note 1. E.T. : Extended Temperature, Normal : Normal Temperature
2. Current value is max.
3. * measured with 30pF test load
Temperature
(°C)
0~70(Normal)
-40~85(E.T.)
0~70(Normal)
-40~85(E.T.)
PIN CONNECTION
A11
A9
A8
A13
/WE
CS2
A15
Vcc
A17
A16
A14
A12
A7
A6
A5
A4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
/OE
A10
/CS1
DQ8
DQ7
DQ6
DQ5
DQ4
Vss
DQ3
DQ2
DQ1
A0
A1
A2
A3
A4
A5
A6
A7
A12
A14
A16
A17
Vcc
A15
CS2
/WE
A13
A8
A9
A11
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
A3
A2
A1
A0
DQ1
DQ2
DQ3
Vss
DQ4
DQ5
DQ6
DQ7
DQ8
/CS1
A10
/OE
sTSOP-I/TSOP-I(Standard)
sTSOP/TSOP-I(Reversed)
PIN DESCRIPTION
Pin Name
/CS1
CS2
/WE
/OE
A0 ~ A17
I/O1 ~ I/O8
Vcc
Vss
Pin Function
Chip Select 1
Chip Select 2
Write Enable
Output Enable
Address Input
Data Input/Output
Power(3.3V or 3.0V)
Ground
BLOCK DIAGRAM
SENSE AMP
A0
ADD INPUT BUFFER
COLUMN DECODER
ROW DECODER
I/O1
OUTPUT BUFFER
I/O8
A17
CONTROL
LOGIC
/CS1
CS2
/WE
/OE
This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any
responsibility for use of circuits described. No patent licenses are implied.
Rev.06 /Jan99
Hyundai Semiconductor
WRITE DRIVER
MEMORY ARRAY
2048x1024
HY62V8200-(I)/HY62U8200-(I) Series
ORDERING INFORMATION
Part No.
HY62V8200LT1
HY62V8200LLT1
HY62V8200LR1
HY62V8200LLR1
HY62V8200LST
HY62V8200LLST
HY62V8200LSR
HY62V8200LLSR
HY62V8200LT1-I
HY62V8200LLT1-I
HY62V8200LR1-I
HY62V8200LLR1-I
HY62V8200LST-I
HY62V8200LLST-I
HY62V8200LSR-I
HY62V8200LLSR-I
HY62U8200LT1
HY62U8200LLT1
HY62U8200LR1
HY62U8200LLR1
HY62U8200LST
HY62U8200LLST
HY62U8200LSR
HY62U8200LLSR
HY62U8200LT1-I
HY62U8200LLT1-I
HY62U8200LR1-I
HY62U8200LLR1-I
HY62U8200LST-I
HY62U8200LLST-I
HY62U8200LSR-I
HY62U8200LLSR-I
Speed
70*/85/100
70*/85/100
70*/85/100
70*/85/100
70*/85/100
70*/85/100
70*/85/100
70*/85/100
70*/85/100
70*/85/100
70*/85/100
70*/85/100
70*/85/100
70*/85/100
70*/85/100
70*/85/100
70*/85/100
70*/85/100
70*/85/100
70*/85/100
70*/85/100
70*/85/100
70*/85/100
70*/85/100
70*/85/100
70*/85/100
70*/85/100
70*/85/100
70*/85/100
70*/85/100
70*/85/100
70*/85/100
Power
L-part
LL-part
L-part
LL-part
L-part
LL-part
L-part
LL-part
L-part
LL-part
L-part
LL-part
L-part
LL-part
L-part
LL-part
L-part
LL-part
L-part
LL-part
L-part
LL-part
L-part
LL-part
L-part
LL-part
L-part
LL-part
L-part
LL-part
L-part
LL-part
Temp.
Package
TSOP-I(Standard)
TSOP-I(Standard)
TSOP-I(Reversed)
TSOP-I(Reversed)
Small TSOP-I(Standard)
Small TSOP-I(Standard)
Small TSOP-I(Reversed)
Small TSOP-I(Reversed)
TSOP-I(Standard)
TSOP-I(Standard)
TSOP-I(Reversed)
TSOP-I(Reversed)
Small TSOP-I(Standard)
Small TSOP-I(Standard)
Small TSOP-I(Reversed)
Small TSOP-I(Reversed)
TSOP-I(Standard)
TSOP-I(Standard)
TSOP-I(Reversed)
TSOP-I(Reversed)
Small TSOP-I(Standard)
Small TSOP-I(Standard)
Small TSOP-I(Reversed)
Small TSOP-I(Reversed)
TSOP-I(Standard)
TSOP-I(Standard)
TSOP-I(Reversed)
TSOP-I(Reversed)
Small TSOP-I(Standard)
Small TSOP-I(Standard)
Small TSOP-I(Reversed)
Small TSOP-I(Reversed)
E.T.
E.T.
E.T.
E.T.
E.T.
E.T.
E.T.
E.T.
E.T.
E.T.
E.T.
E.T.
E.T.
E.T.
E.T.
E.T.
Note 1. E.T. : Extended Temperature, Blank : Normal Temperature
2. * measured with 30pF test load.
Rev.06 /Jan.99
2
HY62V8200-(I)/HY62U8200-(I) Series
ABSOLUTE MAXIMUM RATING (1)
Symbol
V
IN,
V
OUT
V
CC
T
A
Parameter
Voltage on any pin relative to Vss
Voltage on Vcc supply relative to
Vss
Operating Temperature
Rating
-0.2 to 3.9
-0.2 to 4.0
0 to 70
-40 to 85
T
STG
P
D
I
OUT
T
SOLDER
Storage Temperature
Power Dissipation
Data Output Current
Lead Soldering Temperature & Time
-55 to 150
1.0
50
260
•
5
Unit
V
V
°C
°C
°C
W
mA
°C•sec
Remark
HY62V8200
HY62U8200
HY62V8200-I
HY62U8200-I
Note
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent
damage to the device. This is stress rating only and the functional operation of the device under these or
any other conditions above those indicated in the operation of this specification is not implied.
Exposure to the absolute maximum rating conditions for extended period may affect reliability.
RECOMMENDED DC OPERATING CONDITION
Symbol
Vcc
Vss
V
IH
V
IL
Parameter
Supply Voltage
Ground
Input High
Voltage
Input Low Voltage
Product
HY62V8200-(I)
HY62U8200-(I)
HY62V8200-(I)
HY62U8200-(I)
HY62V8200-(I)
HY62U8200-(I)
HY62V8200-(I)
HY62U8200-(I)
Min.
3.0
2.7
0
2.2
-0.2
(1)
Typ.
3.3
3.0
0
-
-
Max.
3.6
3.3
0
Vcc+0.2
0.4
Unit
V
V
V
V
V
Note
1. V
IL
= -1.5V for pulse width less than 30ns
TRUTH TABLE
/CS1
H
X
L
L
L
CS2
X
L
H
H
H
/WE
X
X
H
H
L
/OE
X
X
H
L
X
MODE
Standby
Output Disabled
Read
Write
I/O OPERATION
High-Z
High-Z
High-Z
Data Out
Data In
Current
Isb
Isb, Isb1
Icc
Icc
Icc
Note :
1. H=V
IH
, L=V
IL
, X=don't care
Rev.06 /Jan.99
3
HY62V8200-(I)/HY62U8200-(I) Series
DC ELECTRICAL CHARACTERISTICS
Vcc = 3.3V±10%/3.0V±10%, T
A
= 0°C to 70°C (Normal)/ -40°C to 85°C (E.T.), unless otherwise specified
Sym.
Parameter
Test Condition
Min. Typ. Max. Unit
I
LI
Input Leakage Current
Vss < V
IN
< Vcc
-1
-
1
uA
I
LO
Output Leakage Current
Vss < V
OUT
< Vcc, /CS1 = V
IH
or
-1
-
1
uA
CS2 = V
IL
or
/
OE
=
V
IH
or /WE = V
IL
Icc
Operating Power Supply
/CS1 = V
IL
, CS2 = V
IH,
-
-
5
mA
Current
V
IN
= V
IH
or V
IL,
I
I/O =
0mA
I
CC1
Average Operating
/CS1 = V
IL
CS2 = V
IH,
70ns
-
-
60
mA
Current
Min Duty Cycle = 100%,
85ns
-
-
50
mA
I
I/O =
0mA
100ns
-
-
50
mA
I
SB
TTL Standby Current
/CS1 = V
IH
or CS2 = V
IL
-
-
0.5
mA
(TTL Input)
I
SB1
Standby HY62V8200
/CS1 > Vcc - 0.2V
L
-
-
50
uA
Current
LL
-
-
15
uA
(CMOS
HY62V8200-I
CS2 > 0.2V or
L
-
-
50
uA
Input)
LL
-
-
20
uA
HY62U8200
CS2 > Vcc - 0.2V
L
-
-
50
uA
LL
-
-
15
uA
HY62U8200-I
L
-
50
uA
LL
-
20
uA
V
OL
Output Low Voltage
I
OL
= 2.1mA
-
-
0.4
V
V
OH
Output High Voltage
I
OH =
-1mA
2.2
-
-
V
Note : Typical values are at Vcc = 3.3V/3.0V, T
A
= 25°C
AC CHARACTERISTICS
Vcc = 3.3V±10%/3.0V±10%, T
A
= 0°C to 70°C (Normal)/ -40°C to 85°C (E.T.), unless otherwise specified
-70
-85
-10
# Symbol
Unit
Parameter
Min.
Max. Min. Max. Min. Max.
READ CYCLE
1
tRC
Read Cycle Time
70
-
85
-
100
-
ns
2
tAA
Address Access Time
-
70
-
85
-
100
ns
3
tACS
Chip Select Access Time
-
70
-
85
-
100
ns
4
tOE
Output Enable to Output Valid
-
40
-
45
-
50
ns
5
tCLZ
Chip Select to Output in Low Z
10
-
10
-
10
-
ns
6
tOLZ
Output Enable to Output in Low Z
5
-
5
-
5
-
ns
7
tCHZ
Chip Deselection to Output in High Z
0
20
0
25
0
30
ns
8
tOHZ
Out Disable to Output in High Z
0
20
0
25
0
30
ns
9
tOH
Output Hold from Address Change
15
-
15
-
15
-
ns
WRITE CYCLE
10 tWC
Write Cycle Time
70
-
85
-
100
-
ns
11 tCW
Chip Selection to End of Write
60
-
70
-
80
-
ns
12 tAW
Address Valid to End of Write
60
-
70
-
80
-
ns
13 tAS
Address Set-up Time
0
-
0
-
0
-
ns
14 tWP
Write Pulse Width
50
-
60
-
70
-
ns
15 tWR
Write Recovery Time
0
-
0
-
0
-
ns
16 tWHZ
Write to Output in High Z
0
20
0
25
0
30
ns
17 tDW
Data to Write Time Overlap
35
-
35
-
40
-
ns
18 tDH
Data Hold from Write Time
0
-
0
-
0
-
ns
19 tOW
Output Active from End of Write
5
-
5
-
5
-
ns
Rev.06 /Jan.99
4
HY62V8200-(I)/HY62U8200-(I) Series
AC TEST CONDITIONS
T
A
= 0°C to 70°C (Normal) / -40°C to 85°C (E.T.), unless otherwise specified
PARAMETER
Value
Input Pulse Level
0.4V to 2.2V
Input Rise and Fall Time
5ns
Input and Output Timing Reference Level
1.5V
Output Load
CL = 100pF + 1TTL Load
CL* = 30pF + 1TTL Load
Note
* : Test load is 30pF for 70ns device.
AC TEST LOADS
TTL
CL(1)
Note : 1 Including jig and scope capacitance
CAPACITANCE
(Temp = 25°C, f= 1.0MHz)
Symbol
Parameter
C
IN
Input Capacitance
C
OUT
Output Capacitance
Condition
V
IN
= 0V
V
I/O
= 0V
Max.
8
10
Unit
pF
pF
Note : These parameters are sampled and not 100% tested
Rev.06 /Jan.99
5
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