4Gb: x4, x8 TwinDie DDR2 SDRAM
Features
TwinDie™ DDR2 SDRAM
MT47H1G4 – 64 Meg x 4 x 8 Banks x 2 Ranks
MT47H512M8 – 32 Meg x 8 x 8 Banks x 2 Ranks
Features
• Uses 2Gb Micron die
• Two ranks (includes dual CS#, ODT, and CKE balls)
• Each rank has 8 internal banks for concurrent oper-
ation
• V
DD
= V
DDQ
= +1.8V ±0.1V
• JEDEC-standard 63-ball FBGA
• Low-profile package – 1.35mm MAX thickness
Functionality
The 4Gb (TwinDie™) DDR2 SDRAM uses Micron’s
2Gb DDR2 monolithic die and has similar functionali-
ty. This TwinDie data sheet is intended to provide a
general description, package dimensions, and the
ballout only. Refer to Micron's 2Gb DDR2 data sheet
for complete information or for specifications not in-
cluded in this document.
Options
• Configuration
– 64 Meg x 4 x 8 banks x 2 ranks
– 32 Meg x 8 x 8 banks x 2 ranks
• FBGA package (Pb-free)
– 63-ball FBGA (9mm x 11.5mm) Rev.
C
• Timing – cycle time
1
– 2.5ns @ CL = 5 (DDR2-800)
– 2.5ns @ CL = 6 (DDR2-800)
– 3.0ns @ CL = 5 (DDR2-667)
– 3.75ns @ CL = 4 (DDR2-533)
• Self refresh
– Standard
• Operating temperature
– Commercial (0°C
≤
T
C
≤
85°C)
• Revision
Note:
1. CL = CAS (READ) latency.
Marking
1G4
512M8
WTR
-25E
-25
-3
-37E
None
None
:C
Table 1: Key Timing Parameters
Speed
Grade
-25E
-25
-3
-37E
Data Rate (MT/s)
CL = 3
400
400
400
400
CL = 4
533
533
533
533
CL = 5
800
667
667
n/a
CL = 6
800
800
n/a
n/a
t
RCD
t
RP
t
RC
t
RFC
(ns)
(ns)
(ns)
(ns)
12.5
15
15
15
12.5
15
15
15
55
55
55
55
197.5
197.5
197.5
197.5
Table 2: Addressing
Parameter
Configuration
Refresh count
Row address
Bank address
Column address
1 Gig x 4
64 Meg x 4 x 8 banks x 2 ranks
8K
A[14:0] (32K)
BA[2:0] (8)
A[11, 9:0] (2K)
512 Meg x 8
32 Meg x 8 x 8 banks x 2 ranks
8K
A[14:0] (32K)
BA[2:0] (8)
A[9:0] (1K)
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mt47h1g_64m_32m_twindie.pdf - Rev. I 01/14 EN
1
Products and specifications discussed herein are subject to change by Micron without notice.
Micron Technology, Inc. reserves the right to change products or specifications without notice.
©
2006 Micron Technology, Inc. All rights reserved.
4Gb: x4, x8 TwinDie DDR2 SDRAM
Ball Assignments and Descriptions
Ball Assignments and Descriptions
Figure 1: 63-Ball FBGA – x4, x8 Ball Assignments (Top View)
1
A
B
C
D
E
V
DDL
V
DDQ
NF, DQ4
2
3
4
5
6
7
8
9
V
DD
NF, NU/RDQS#
V
SS
NF, DQ6
V
SSQ
DQS
DQS#/NU V
DDQ
V
SSQ
DQ0
NF, DQ7
V
SSQ
DM, RDQS
DQ1
V
DDQ
DQ3
V
DDQ
DQ2
V
DDQ
NF, DQ5
V
SSQ
V
REF
CKE0
V
SSQ
CK
V
SS
WE#
V
SSDL
RAS#
V
DD
ODT0
F
CK#
G
BA2
BA0
BA1
CAS#
CS0#
CS1#
H
J
K
L
CKE1
A10
A1
A2
A0
V
DD
ODT1
V
SS
A3
A5
A6
A4
A7
A9
A11
A8
V
SS
V
DD
A12
A14
RFU
A13
Note:
1. Dark balls (with ring) designate balls that differ from the monolithic versions.
PDF: 09005aef8227ee4d
mt47h1g_64m_32m_twindie.pdf - Rev. I 01/14 EN
2
Micron Technology, Inc. reserves the right to change products or specifications without notice.
©
2006 Micron Technology, Inc. All rights reserved.
4Gb: x4, x8 TwinDie DDR2 SDRAM
Ball Assignments and Descriptions
Table 3: FBGA 63-Ball Descriptions
Symbol
A[14:0]
Type
Input
Description
Address inputs:
Provide the row address for ACTIVATE commands, and the column ad-
dress and auto precharge bit (A10) for READ/WRITE commands, to select one location out
of the memory array in the respective bank. A10 sampled during a PRECHARGE com-
mand determines whether the PRECHARGE applies to one bank (A10 LOW, bank selected
by BA[2:0]) or all banks (A10 HIGH). The address inputs also provide the op-code during a
LOAD MODE command.
Bank address inputs:
BA[2:0] define to which bank an ACTIVATE, READ, WRITE, or PRE-
CHARGE command is being applied. BA[2:0] define which mode register including MR,
EMR, EMR(2), and EMR(3) is loaded during the LOAD MODE command.
Clock:
CK and CK# are differential clock inputs. All address and control input signals are
sampled on the crossing of the positive edge of CK and negative edge of CK#. Output
data (DQ and DQS/DQS#) is referenced to the crossings of CK and CK#.
Clock enable:
CKE (registered HIGH) activates and CKE (registered LOW) deactivates
clocking circuitry on the DDR2 SDRAM. The specific circuitry that is enabled/disabled is
dependent on the DDR2 SDRAM configuration and operating mode. CKE LOW provides
precharge power-down and SELF REFRESH operations (all banks idle), or ACTIVATE pow-
er-down (row active in any bank). CKE is synchronous for power-down entry, power-
down exit, output disable, and for SELF REFRESH entry. CKE is asynchronous for SELF RE-
FRESH exit. Input buffers (excluding CK, CK#, CKE, and ODT) are disabled during POWER-
DOWN. Input buffers (excluding CKE) are disabled during SELF REFRESH. CKE is an
SSTL_18 input but will detect a LVCMOS LOW level once V
DD
is applied during first pow-
er-up. After V
REF
has become stable during the power-on and initialization sequence, it
must be maintained for proper operation of the CKE receiver. For proper SELF-REFRESH
operation, V
REF
must be maintained.
Chip select:
CS# enables (registered LOW) and disables (registered HIGH) the command
decoder. All commands are masked when CS# is registered HIGH. CS# provides for exter-
nal bank selection on systems with multiple ranks. CS# is considered part of the com-
mand code.
Input data mask:
DM is an input mask signal for write data. Input data is masked when
DM is sampled HIGH along with that input data during a WRITE access. DM is sampled on
both edges of DQS. Although DM balls are input-only, the DM loading is designed to
match that of DQ and DQS balls.
On-die termination:
ODT (registered HIGH) enables termination resistance internal to
the DDR2 SDRAM. When enabled, ODT is only applied to each of the following balls:
DQ[7:0], DQS, DQS#, and DM. The ODT input will be ignored if disabled via the LOAD
MODE command.
Command inputs:
RAS#, CAS#, and WE# (along with CS#) define the command being
entered.
Data input/output:
Bidirectional data bus for x4 configuration.
Data input/output:
Bidirectional data bus for x8 configuration.
Data strobe:
Output with read data, input with write data for source synchronous oper-
ation. Edge-aligned with read data, center-aligned with write data. DQS# is only used
when differential data strobe mode is enabled via the LOAD MODE command.
BA[2:0]
Input
CK, CK#
Input
CKE[1:0]
Input
CS#
Input
DM
Input
ODT[1:0]
Input
RAS#, CAS#, WE#
DQ[3:0]
DQ[7:0]
DQS, DQS#
Input
I/O
I/O
I/O
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mt47h1g_64m_32m_twindie.pdf - Rev. I 01/14 EN
3
Micron Technology, Inc. reserves the right to change products or specifications without notice.
©
2006 Micron Technology, Inc. All rights reserved.
4Gb: x4, x8 TwinDie DDR2 SDRAM
Ball Assignments and Descriptions
Table 3: FBGA 63-Ball Descriptions (Continued)
Symbol
RDQS, RDQS#
Type
I/O
Description
Redundant data strobe:
For the x8 configuration only. RDQS is enabled/disabled via
the load mode command to the extended mode register (EMR). When RDQS is enabled,
RDQS is output with read data only and is ignored during write data. When RDQS is disa-
bled, ball B3 becomes data mask (see DM ball). RDQS# is only used when RDQS is enabled
and
differential data strobe mode is enabled.
Power supply:
1.8V ±0.1V.
DQ power supply:
1.8V ±0.1V. Isolated on the device for improved noise immunity.
DLL power supply:
1.8V ±0.1V.
SSTL_18 reference voltage (V
DDQ
/2).
Ground.
DLL ground:
Isolated on the device from V
SS
and V
SSQ
.
DQ ground:
Isolated on the device for improved noise immunity.
No function:
These balls are no function on the x4 configuration.
Not used:
For the x8 configuration only. If EMR(E10) = 0, A2 = RDQS# and A8 = DQS#. If
EMR(E10) = 1, A2 and A8 are not used.
Reserved for future use.
V
DD
V
DDQ
V
DDL
V
REF
V
SS
V
SSDL
V
SSQ
NF
NU
RFU
Supply
Supply
Supply
Supply
Supply
Supply
Supply
–
–
–
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mt47h1g_64m_32m_twindie.pdf - Rev. I 01/14 EN
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Micron Technology, Inc. reserves the right to change products or specifications without notice.
©
2006 Micron Technology, Inc. All rights reserved.
4Gb: x4, x8 TwinDie DDR2 SDRAM
Functional Description
Functional Description
The 4Gb (TwinDie) DDR2 SDRAM is a high-speed, CMOS dynamic random access
memory device containing 4,294,967,296 bits and internally configured as two 8-bank
2Gb DDR2 SDRAM devices.
Although each die is tested individually within the dual-die package, some TwinDie test
results may vary from a like-die tested within a monolithic die package.
Each DDR2 SDRAM die uses a double data rate architecture to achieve high-speed op-
eration. The DDR2 architecture is essentially a 4n-prefetch architecture, with an inter-
face designed to transfer two data words per clock cycle at the I/O balls. A single read or
write access consists of a single 4n-bit-wide, one-clock-cycle data transfer at the inter-
nal DRAM core and four corresponding
n-bit-wide,
one-half-clock-cycle data transfers
at the I/O balls.
Addressing of the TwinDie is identical to the monolithic device. Additionally, multiple
chip selects select the desired rank.
This TwinDie data sheet is intended to provide a general description, package dimen-
sions, and the ballout only. Refer to the Micron 2Gb DDR2 data sheet for complete in-
formation regarding individual die initialization, register definition, command descrip-
tions, and die operation.
PDF: 09005aef8227ee4d
mt47h1g_64m_32m_twindie.pdf - Rev. I 01/14 EN
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Micron Technology, Inc. reserves the right to change products or specifications without notice.
©
2006 Micron Technology, Inc. All rights reserved.
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