Caution 1) Absolute maximum ratings represent the value which cannot be exceeded for any length of time.
Caution 2) Even when the device is used within the range of absolute maximum ratings, as a result of continuous usage under high temperature, high current,
high voltage, or drastic temperature change, the reliability of the IC may be degraded. Please contact us for the further details.
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed,
damage may occur and reliability may be affected.
Recommended Operating Conditions
at Ta = 25C
Parameter
Supply voltage range
5V constant voltage output current
LD pin applied voltage
LD pin output current
FG pin applied voltage
FG pin output current
HB pin output current
Symbol
VCC
IREG
VLD
ILD
VFG
IFG
IHB
Conditions
Ratings
10 to 35
0 to -30
0 to 5.5
0 to 15
0 to 5.5
0 to 15
0 to -30
Unit
V
mA
V
mA
V
mA
mA
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended
Operating Ranges limits may affect device reliability.
Electrical Characteristics
at Ta
½
25C, VCC = 24V
Ratings
Parameter
Current drain
Symbol
ICC1
ICC2
5V Constant Voltage Output
Output voltage
Line regulation
Load regulation
Temperature coefficient
Output Block
Output ON resistance
Output leakage current
Lower side Diode forward voltage
Upper side Diode forward voltage
Charge Pump Output
(VG pin)
Output voltage
CP1 pin
Output ON resistance (High level)
Output ON resistance (Low level)
VOH(CP1)
VOL(CP1)
ICP1 = -2mA, Design target value *
ICP1 = 2mA
500
300
700
400
VGOUT
VCC+4.9
V
RON
IOleak
VD1
VD2
IO = 1A , Sum of the lower and upper side
outputs
Design target value *
ID = -1A
ID = 1A
1.0
1.0
10
1.35
1.35
A
V
V
1.5
1.9
VREG
VREG1
VREG2
VREG3
VCC = 10 to 35V
IO = -5 to -20mA
Design target value *
4.65
5.0
20
25
0
5.35
100
60
V
mV
mV
mV/C
In a stop state
Conditions
min
typ
5.5
1.0
max
6.5
1.5
mA
mA
Unit
* Design target value, Do not measurement.
Continued on next page.
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2
LV8112VB
Continued from preceding page.
Ratings
Parameter
Hall Amplifier Block
Input bias current
Common mode input voltage range
Hall input sensitivity
Hysteresis
Input voltage L
H
Input voltage H
L
Hall Bias
(HB pin) P-channel Output
Output voltage ON resistance
Output leakage current
FG Amplifier Schmitt Block
(IN1)
Input amplifier gain
Input hysteresis (H
L)
Input hysteresis (L
H)
Hysteresis
FGFIL pin
High level output voltage
Low level output voltage
External capacitor charge current
External capacitor discharge current
Amplitude
FG Output
Output ON resistance
Output leakage current
PWM Oscillator
High level output voltage
Low level output voltage
External capacitor charge current
Oscillation frequency
Amplitude
Recommended operation frequency
range
CSD Oscillation Circuit
High level output voltage
Low level output voltage
Amplitude
External capacitor charge current
External capacitor discharge current
Oscillation frequency
Phase comparing output
Output ON resistance (high level)
Output ON resistance (low level)
Phase Lock Detection Output
Output ON resistance
Output leakage current
Error Amplifier Block
Input offset voltage
Input bias current
High level output voltage
Low level output voltage
DC bias level
VIO(ER)
IB(ER)
VOH(ER)
VOL(ER)
VB(ER)
IEI = -100A
IEI = 100A
Design target value *
-10
-1
EI+0.7
EI-1.75
-5%
EI+0.85
EI-1.6
VREG/2
+10
+1
EI+1.0
EI-1.45
5%
mV
A
V
V
V
VOL(LD)
IL(LD)
ILD = 10mA
VO = 5.5V
20
30
10
A
VPDH
VPDL
IOH = -100A
IOL = 100A
500
500
700
700
VOH(CSD)
VOL(CSD)
V(CSD)
ICHG1(CSD) VCHG1 = 2.0V
ICHG2(CSD) VCHG2 = 2.0V
f(CSD)
C = 0.068F, Design target value *
2.7
0.8
1.75
-14
8
30
3.0
1.0
2.0
-10
11
40
3.3
1.2
2.25
-6
14
50
V
V
Vp-p
A
A
Hz
VOH(PWM)
VOL(PWM)
ICHG(PWM)
f(PWM)
V(PWM)
fOPR
VPWM = 2V
C = 150pF
2.95
1.3
-90
180
1.5
15
3.2
1.5
-70
225
1.7
3.45
1.7
-50
270
1.9
300
V
V
A
kHz
Vp-p
kHz
VOL(FG)
IL(FG)
IFG = 7mA
VO = 5.5V
20
30
10
A
VOH(FGFIL)
VOL(FGFIL)
ICHG1
ICHG2
V(FGFIL)
VCHG1 = 1.5V
VCHG2 = 1.5V
2.7
0.75
-5
3
1.95
3.0
0.85
-4
4
2.15
3.3
0.95
-3
5
2.35
V
V
A
A
Vp-p
GFG
VSHL(FGS)
VSLH(FGS)
VFGL
Design target value *
Input referred, Design target value *
Input referred, Design target value *
Input referred, Design target value *
5
0
10
10
times
mV
mV
mV
VOL(HB)
IL(HB)
IHB = -20mA
VO = 0V
20
30
10
A
V
IN(HA)
VSLH
VSHL
IHB(HA)
VICM
-2
0.5
80
15
24
12
-12
42
-0.5
VREG-2.0
A
V
mVp-p
mV
mV
mV
Symbol
Conditions
min
typ
max
Unit
* Design target value, Do not measurement.
Continued on next page.
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3
LV8112VB
Continued from preceding page.
Ratings
Parameter
Current Control Circuit
Drive gain
GDF
While phase locked
0.5
0.55
0.6
times
Symbol
Conditions
min
typ
max
Unit
Current Limiter Circuit
(pins RF and RFS)
Limiter voltage
Under-voltage Protection
Operation voltage
Hysteresis
CLD Circuit
External capacitor charge current
Operation voltage
Thermal Shutdown Operation
Thermal shutdown operation
temperature
Hysteresis
CLK pin
External input frequency
High level input voltage
Low level input voltage
Input open voltage
Hysteresis
High level input current
Low level input current
CSDSEL pin
High level input voltage
Low level input voltage
Input open voltage
High level input current
Low level input current
S/S pin
High level input voltage
Low level input voltage
Input open voltage
Hysteresis
High level input current
Low level input current
BRSEL pin
High level input voltage
Low level input voltage
Input open voltage
High level input current
Low level input current
F/R pin
High level input voltage
Low level input voltage
Input open voltage
High level input current
Low level input current
VIH(FR)
VIL(FR)
VIO(FR)
IIH(FR)
IIL(FR)
VF/R = VREG
VF/R = 0V
2.0
0
VREG-0.5
-10
-110
0
-85
VREG
1.0
VREG
+10
-60
V
V
V
A
A
VIH(BRSEL)
VIL(BRSEL)
VIO(BRSEL)
IIH(BRSEL)
IIL(BRSEL)
VBRSEL = VREG
VBRSEL = 0V
2.0
0
VREG-0.5
-10
-110
0
-85
VREG
1.0
VREG
+10
-60
V
V
V
A
A
VIH(SS)
VIL(SS)
VIO(SS)
VIS(SS)
IIH(SS)
IIL(SS)
VS/S = VREG
VS/S =0V
2.0
0
VREG-0.5
0.2
-10
-110
0.3
0
-85
VREG
1.0
VREG
0.4
+10
-60
V
V
V
V
A
A
VIH(CSD)
VIL(CSD)
VIO(CSD)
IIH(CSD)
IIL(CSD)
VCSDSEL = VREG
VCSDSEL = 0V
2.0
0
VREG-0.5
-10
-110
0
-85
VREG
1.0
VREG
+10
-60
V
V
V
A
A
fI(CLK)
VIH(CLK)
VIL(CLK)
VIO(CLK)
VIS(CLK)
IIH(CLK)
IIL(CLK)
VCLK = VREG
VCLK = 0V
0.1
2.0
0
VREG-0.5
0.2
-10
-110
0.3
0
-85
10
VREG
1.0
VREG
0.4
+10
-60
kHz
V
V
V
V
A
A
TSD
Design target value (Junction temperature)
30
C
TSD
Design target value (Junction temperature)
150
175
C
ICLD
VH(CLD)
VCLD = 0V
-4.5
3.25
-3.0
3.5
-1.5
3.75
A
V
VSD
VSD
8.3
0.2
8.7
0.35
9.1
0.5
V
V
VRF
0.465
0.515
0.565
V
* Design target value, Do not measurement.
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be
indicated by the Electrical Characteristics if operated under different conditions.
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