PCX7457VG933NC datasheet, PDF - EEWORLD Datasheet

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PCX7457VG933NC: DescriptionRISC Microprocessor, 32-Bit, 933MHz, CMOS, CBGA483, 29 X 29 MM, 3.22 MM HEIGHT, 1.27 MM PITCH, CERAMIC, BGA-483; CategoryThe embedded processor and controller Microcontrollers and processors; File Size1001KB，59 Pages; Manufacturere2v technologies

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PCX7457VG933NC Overview

RISC Microprocessor, 32-Bit, 933MHz, CMOS, CBGA483, 29 X 29 MM, 3.22 MM HEIGHT, 1.27 MM PITCH, CERAMIC, BGA-483

PCX7457VG933NC Parametric

Parameter Name	Attribute value
Maker	e2v technologies
Parts packaging code	BGA
package instruction	BGA,
Contacts	483
Reach Compliance Code	compliant
ECCN code	3A001.A.3
Other features	ALSO OPERATES AT 1.3V SUPPLY
Address bus width	36
bit size	32
boundary scan	YES
maximum clock frequency	167 MHz
External data bus width	64
Format	FLOATING POINT
Integrated cache	YES
JESD-30 code	S-CBGA-B483
length	29 mm
low power mode	YES
Number of terminals	483
Package body material	CERAMIC, METAL-SEALED COFIRED
encapsulated code	BGA
Package shape	SQUARE
Package form	GRID ARRAY
Certification status	Not Qualified
Maximum seat height	3.2 mm
speed	933 MHz
Maximum supply voltage	1.15 V
Minimum supply voltage	1.05 V
Nominal supply voltage	1.1 V
surface mount	YES
technology	CMOS
Terminal form	BALL
Terminal pitch	1.27 mm
Terminal location	BOTTOM
width	29 mm
uPs/uCs/peripheral integrated circuit type	MICROPROCESSOR, RISC

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PC7457

PowerPC RISC Microprocessor

Datasheet

Features

•

3000 Dhrystone 2.1 MIPS at 1.3 GHz

Selectable Bus Clock (30 CPU Bus Dividers up to 28x)

13 Selectable Core-to-L3 Frequency Divisors

Selectable MPx/60x Interface Voltage (1.8V, 2.5V)

Selectable L3 Interface of 1.8V or 2.5V

Typical 12.6W at 1 GHz at V

= 1.3V; 8.3W at 1 GHz at V

= 1.1V,

Full Operating Conditions

Nap, Doze and Sleep Modes for Power Saving

Superscalar (Four Instructions Fetched Per Clock Cycle)

4 GB Direct Addressing Range

Virtual Memory: 4 Hexabytes (2

)

64-bit Data and 36-bit Address Bus Interface

Integrated L1: 36 KB Instruction and 32 KB Data Cache

Integrated L2: 512 KB

11 Independent Execution Units and Three Register Files

Write-back and Write-through Operations

INT

Max = 1 GHz (1.2 GHz to be Confirmed)

BUS

Max = 133 MHz/166 MHz

Description

The PC7457 is implementations of the PowerPC

microprocessor family of reduced instruction set computer (RISC) micro-

processors. This document describes pertinent electrical and physical characteristics of the PC7457.

The PC7457 is the fourth implementation of the fourth generation (G4) microprocessors from Freescale. The PC7457

implements the full PowerPC 32-bit architecture and is targeted at networking and computing systems applications. The

PC7457 consists of a processor core, a 512 Kbyte L2, and an internal L3 tag and controller which support a glueless back-

side L3 cache through a dedicated high-bandwidth interface.

The core is a high-performance superscalar design supporting a double-precision floating-point unit and a SIMD multime-

dia unit. The memory storage subsystem supports the MPX bus interface to main memory and other system resources.

The L3 interface supports 1, 2, or 4M bytes of external SRAM for L3 cache and/or private memory data. For systems imple-

menting 4M bytes of SRAM, a maximum of 2M bytes may be used as cache; the remaining 2M bytes must be private

memory.

Note that the PC7457 is a footprint-compatible, drop-in replacement in a PC7455 application if the core power supply is

1.3V.

Visit our website: www.e2v.com

for the latest version of the datasheet

e2v semiconductors SAS 2007

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