PPC5643LF0VLQ1 datasheet, PDF - EEWORLD Datasheet

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PPC5643LF0VLQ1: Description32-BIT, FLASH, 120MHz, MICROCONTROLLER, PQFP144, 20 X 20 MM, 1.40 MM HEIGHT, 0.50 MM PITCH, ROHS COMPLIANT, LQFP-144; CategoryThe embedded processor and controller Microcontrollers and processors; File Size735KB，126 Pages; ManufacturerNXP; Websitehttps://www.nxp.com; Environmental Compliance

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PPC5643LF0VLQ1 Overview

32-BIT, FLASH, 120MHz, MICROCONTROLLER, PQFP144, 20 X 20 MM, 1.40 MM HEIGHT, 0.50 MM PITCH, ROHS COMPLIANT, LQFP-144

PPC5643LF0VLQ1 Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Maker	NXP
Parts packaging code	QFP
package instruction	20 X 20 MM, 1.40 MM HEIGHT, 0.50 MM PITCH, ROHS COMPLIANT, LQFP-144
Contacts	144
Reach Compliance Code	compliant
ECCN code	3A991.A.2
Has ADC	YES
Other features	IT ALSO OPERATES AT 4.5V TO 5.5V
Address bus width
bit size	32
maximum clock frequency	40 MHz
DAC channel	NO
DMA channel	YES
External data bus width
JESD-30 code	S-PQFP-G144
length	20 mm
Number of I/O lines	98
Number of terminals	144
Maximum operating temperature	105 °C
Minimum operating temperature	-40 °C
PWM channel	YES
Package body material	PLASTIC/EPOXY
encapsulated code	LFQFP
Encapsulate equivalent code	QFP144,.87SQ,20
Package shape	SQUARE
Package form	FLATPACK, LOW PROFILE, FINE PITCH
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
power supply	3.3 V
Certification status	Not Qualified
RAM (bytes)	131072
rom(word)	1048576
ROM programmability	FLASH
Maximum seat height	1.6 mm
speed	120 MHz
Maximum supply voltage	3.6 V
Minimum supply voltage	3 V
Nominal supply voltage	3.3 V
surface mount	YES
technology	BIPOLAR
Temperature level	INDUSTRIAL
Terminal form	GULL WING
Terminal pitch	0.5 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	NOT SPECIFIED
width	20 mm
uPs/uCs/peripheral integrated circuit type	MICROCONTROLLER

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Freescale Semiconductor

Data Sheet: Advance Information

Document Number: MPC5643L

Rev. 7, 3/2011

MPC5643L

Qorivva MPC5643L

Microcontroller Data Sheet

• High-performance e200z4d dual core

– 32-bit Power Architecture

technology CPU

– Core frequency as high as 120 MHz

– Dual issue five-stage pipeline core

– Variable Length Encoding (VLE)

– Memory Management Unit (MMU)

– 4 KB instruction cache with error detection code

– Signal processing engine (SPE)

• Memory available

– 1 MB flash memory with ECC

– 128 KB on-chip SRAM with ECC

– Built-in RWW capabilities for EEPROM emulation

• SIL3/ASILD innovative safety concept: LockStep mode

and Fail-safe protection

– Sphere of replication (SoR) for key components (such as

CPU core, eDMA, crossbar switch)

– Fault collection and control unit (FCCU)

– Redundancy control and checker unit (RCCU) on

outputs of the SoR connected to FCCU

– Boot-time Built-In Self-Test for Memory (MBIST) and

Logic (LBIST) triggered by hardware

– Boot-time Built-In Self-Test for ADC and flash memory

triggered by software

– Replicated safety enhanced watchdog

– Replicated junction temperature sensor

– Non-maskable interrupt (NMI)

– 16-region memory protection unit (MPU)

– Clock monitoring units (CMU)

– Power management unit (PMU)

– Cyclic redundancy check (CRC) unit

• Decoupled Parallel mode for high-performance use of

replicated cores

• Nexus Class 3+ interface

• Interrupts

– Replicated 16-priority controller

– Replicated 16-channel eDMA controller

MAPBGA–225

15 mm x 15 mm

QFN12

##_mm_x_##mm

SOT-343R

##_mm_x_##mm

144 LQFP

(20 x 20 x 1.4 mm)

TBD

PKG-TBD

## mm x ## mm

257 MAPBGA

(14 x 14 x 0.8 mm)

• GPIOs individually programmable as input, output or

special function

• Three 6-channel general-purpose eTimer units

• 2 FlexPWM units

– Four 16-bit channels per module

• Communications interfaces

– 2 LINFlexD channels

– 3 DSPI channels with automatic chip select generation

– 2 FlexCAN interfaces (2.0B Active) with 32 message

objects

– FlexRay module (V2.1 Rev. A) with 2 channels, 64

message buffers and data rates up to 10 Mbit/s

• Two 12-bit analog-to-digital converters (ADCs)

– 16 input channels

– Programmable cross triggering unit (CTU) to

synchronize ADCs conversion with timer and PWM

• Sine wave generator (D/A with low pass filter)

• On-chip CAN/UART bootstrap loader

• Single 3.0 V to 3.6 V voltage supply

• Ambient temperature range –40 °C to 125 °C

• Junction temperature range –40 °C to 150 °C

This document contains information on a product under development. Freescale reserves the

right to change or discontinue this product without notice.

Preliminary—Subject to Change Without Notice

Introduction

1.1

Introduction

Document overview

This document describes the features of the family and options available within the family members, and highlights important

electrical and physical characteristics of the devices.

This document provides electrical specifications, pin assignments, and package diagrams for the Qorivva MPC5643L series of

microcontroller units (MCUs). For functional characteristics, see the

MPC5643L Microcontroller Reference Manual.

For use

of the MPC5643Lin a fail-safe system according to safety standard IEC 61508, see the

Safety Application Guide for MPC5643L.

The MPC5643L MCU series is available in two silicon versions, or “cuts”. These are referred to as “cut1” and “cut2” throughout

this document. Functional differences between the two cuts are clearly identified with the labels “cut1” and “cut2”.

1.2

Description

The Qorivva MPC5643L series microcontrollers are system-on-chip devices that are built on Power Architecture technology

and contain enhancements that improve the architecture’s fit in embedded applications, include additional instruction support

for digital signal processing (DSP) and integrate technologies such as an enhanced time processor unit, enhanced queued

analog-to-digital converter, Controller Area Network, and an enhanced modular input-output system.

The MPC5643L family of 32-bit microcontrollers is the latest achievement in integrated automotive application controllers. It

belongs to an expanding range of automotive-focused products designed to address electrical hydraulic power steering (EHPS),

electric power steering (EPS) and airbag applications. The advanced and cost-efficient host processor core of the MPC5643L

automotive controller family complies with the Power Architecture embedded category. It operates at speeds as high as

120 MHz and offers high-performance processing optimized for low power consumption. It capitalizes on the available

development infrastructure of current Power Architecture devices and is supported with software drivers, operating systems and

configuration code to assist with users’ implementations.

1.3

Device comparison

Table 1. MPC5643L device summary

Feature

CPU

Type

Architecture

Execution speed

DMIPS intrinsic performance

SIMD (DSP + FPU)

MMU

Instruction set PPC

Instruction set VLE

Instruction cache

MPU-16 regions

Semaphore unit (SEMA4)

Buses

Core bus

Internal periphery bus

MPC5643L

2 × e200z4

(in lock-step or decoupled operation)

Harvard

0–120 MHz (+2% FM)

>240 MIPS

Yes

16 entry

Yes

4 KB, EDC

Yes, replicated module

Yes

AHB, 32-bit address, 64-bit data

32-bit address, 32-bit data

MPC5643L Microcontroller Data Sheet, Rev. 7

Freescale Semiconductor

Preliminary—Subject to Change Without Notice

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