PCA844 datasheet, PDF - EEWORLD Datasheet

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PCA844: DescriptionRead Channel, 1 Channel, PQFP64, PLASTIC, QFP-64; CategoryAnalog mixed-signal IC Drivers and interfaces; File Size154KB，11 Pages; ManufacturerZarlink Semiconductor (Microsemi); Websitehttp://www.zarlink.com/

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PCA844 Overview

Read Channel, 1 Channel, PQFP64, PLASTIC, QFP-64

PCA844 Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	Zarlink Semiconductor (Microsemi)
package instruction	QFP,
Reach Compliance Code	unknown
Drive type	OPTICAL
Interface integrated circuit type	READ CHANNEL
JESD-30 code	S-PQFP-G64
Humidity sensitivity level	1
Number of channels	1
Number of functions	1
Number of terminals	64
Maximum operating temperature	70 °C
Minimum operating temperature
Package body material	PLASTIC/EPOXY
encapsulated code	QFP
Package shape	SQUARE
Package form	FLATPACK
Peak Reflow Temperature (Celsius)	225
Certification status	Not Qualified
Maximum supply voltage	5.5 V
Minimum supply voltage	4.5 V
Nominal supply voltage	5 V
surface mount	YES
Temperature level	COMMERCIAL
Terminal form	GULL WING
Terminal location	QUAD
Maximum time at peak reflow temperature	NOT SPECIFIED

PCA844 Preview

THIS DOCUMENT IS FOR MAINTENANCE

PURPOSES ONLY AND IS NOT

RECOMMENDED FOR NEW DESIGNS

PCA844

July 1993

PRELIMINARY INFORMATION

DS3827 -1.0

PCA844

SINGLE ZONE MODD READ CHANNEL CHIP

FOR DATA RATES BETWEEN 5 AND 15 MBITS/SEC

GENERAL DESCRIPTION

The PCA844 is a low power monolithic mixed signal fully-

integrated Read Channel IC for use in optical disk drive (MODD)

applications. It is designed for use in drives with a single zone

facility. The data rate handling capability of the chip can be

externally selected for the data to be accessed at a rate of

between 5 and 15 Mbits/sec. The chip requires only a single 5

volt ±10% power supply.

It contains all the necessary Read Channel functions;

including AGC Loop, Programmable Active Bessel Filter, Pulse

Detector, Sector Mark Detector and Phase Locked Loop; to

interface with the head pre-amplifiers and data controller and

ENDEC functions. The architecture of the chip is designed such

as to provide the maximum amount of flexibility for different drive

electronics designs and partitioning, whilst minimizing the number

of external components required.

Data is input to the PCA844 from the laser head photodiodes

via current-to-voltage conversion pre-amplifiers. This data would

usually be in the form of differential signals, however, the chip

is also capable of handling single ended input signals by tying

one set of data input to a reference voltage. The use of

differential input signal design techniques significantly reduces

noise within the circuitry.

Dual AGC inputs are provided for the ROM data (read only

area of the disk) and for the MO data (read and write area)

signals. On the PCA844 the ROM input signal range has been

set at 70mV to 600mV and the MO range at 35mV to 300mV

(peak to peak differential). On-chip circuitry regenerates the

digital sector mark signal from a low-level analog input.

The outputs of the AGCs are multiplexed into a full 7th order

Bessel Filter. This filtering is incorporated on-chip along with the

necessary programmable cut-off and boost functions for the

range of data rates supported by the chip. The boost can be

used to equalise the higher frequency components in the MODD

signal.

The Filter provides the normal low-pass and differentiated

outputs used by the on-chip pulse position detector. This detector

generates RAWDATA pulses for clock and data recovery in the

phase-lock loop.

A full functional block diagram of the PCA844 will be found

in Figure 1.

FEATURES

Single rail 5V ±10% operation

5 to 15 Mbits/sec selectable data rates

Low power plus power down modes

Compatible with 2,7 RLL coding

Dual AGC functions for ROM and MO data

On-chip Filtering

Programmable cut-off and boost

Sector Mark signal regeneration

MODD Pulse Detector

PLL with on-chip timing components

Data Synchroniser

Preamble Detection to (8 or 16 x 3T pattern)

64 pin Plastic Quad Flat Pack package

PCA844

BLOCK DIAGRAM

GNDFILT

QUALIFIER

LOGIC

GNDANA

GNDDIG

GNDPLL

AGCHOLD

NTEST

RAGCMO

PULEN

POWER

DOWN

SYNCEN

RAGCCD

VGA

ZCOMP

MO+

MO-

BOOST

MUX

(equalisation)

(10:1)

7th ORDER

BESSEL FILTER

res

ZCOMP

AGC

HOLD

LOGIC

SQUELCH

VIM

VGA

(10:1)

AGC

Loop

VACREF

HIPASS

I/V

AMP

CD+

CD-

CAGCCD

DIFFP

DIFFN

CONT

COMP

LOPASS

PLLBIAS

Pulse

Detector

AGC

Control

CONT

COMP

NORM

I/V

AMP

RESET

PRESEL

PREDET

PREAMBLE

DETECTOR

(8 or 16 x 3T)

SMINP

SMINN

ITRM

TRACKING

MONOSTABLE

DATA

SYNCHRONISER

SYNCLK

PHASE

DETECT

CLAMP DOWN

SMEX1

SMEX2

RDGATE

dV/dt

SIN

RIN

SYNCDAT

CHARGE

PUMP

CLAMP

CLK

Figure 1. PCA844 Functional Block Diagram

Detector

MUX

LOGIC

ZCOMP

SMTHRESH SMDATA RAWDATA REFCLK

Sector

FIXED

Mark

MONO

CLAMP

LOGIC

SMDIFFN

SMDIFFP

ZCOMP

VCO

IVCO

Phase-

Locked Loop

IBIAS

VCOI CEN CP2

CP1

LOOP

FILT

CP3

PCA844

DEVICE MAXIMUM RATING

Parameter

All Inputs

Operating Temperature Range

Storage Temperature

-0.3

-55

Test Conditions

Min.

Typ.

Max.

+0.3

+70

+150

Units

°C

POWER

Parameter

Operating Voltage Range

Supply Current Mode:

Sleep

Pulse Detect. Enabled

Full Power Up

Test Conditions

all V

SYNCEN

PULEN

Min.

4.5

Typ.

5.0

Max.

5.5

Units

120

Note

: Supply currents are calculated with all inputs high, and no load on the outputs.

DIGITAL INPUTS AND OUTPUTS

Digital circuit characteristics over the operating temperature and voltage range.

Parameter

TTL Inputs

Low Level Input Voltage

High Level Input Voltage

Low Level Input Current

High Level Input Current

TTL Outputs

Low Level Output Voltage

High Level Output Voltage

Output Source Current

Output Sink Current

Test Conditions

Min.

Typ.

Max.

Units

2.0

= 0.4

= V

0.8

200

µA

= 4mA

= -400µA

= 2.4

= 0.5V

0.5

2.4

PCA844

AGC LOOP AND FILTER

There are two independent AGC amplifiers which accept

input signals from the read only (CD) and the read/write (MO)

parts of the disk. The amplifier outputs are multiplexed into a

filter which has a single 7th order low pass Bessel output

(NORM), and a differential differentiated out (DIFFP, DIFFN).

These outputs are AC coupled to the pulse detector. The

filter is on chip and has programmable bandwidth and boost.

The TTL input IPSEL multiplexes the AGC inputs and

selects the appropriate AGC control voltage. When IPSEL=1,

MO is active; when IPSEL=0, CD is active.

The single-ended output of the filter NORM is passed to the

AGC control comparators and compared with external AGCSET

voltage which defines the level of the peaks at PULDETIN. The

output of the comparators, CAGCMO & CAGCCD are gain

control voltages for the AGC amplifier. The rate of attack and

decay of these voltages can be set set independently by the

external resistors and capacitors on pins RAGCMO/CD and

CAGCMO/CD.

For the comparator which is not selected by IPSEL at any

time, the pins CAGC and RAGC will be high impedance to hold

the current gain setting for that channel. In addition, bothAGC

control voltages may be held simultaneously by taking the TTL

input AGCHOLD high.

The TTL input SQUELCH when high, reduces the gain of

AGC amplifier to minimum. The input VIMP, when high,

introduces a low impedance between the AGC inputs.

The internally generated reference VACREF is a low

impedance voltage source of V

/2, used to bias the inputs to the

pulse detector. The pin must be externally decoupled and set up

so that a minimum of current is sourced from the pin. The pin

cannot sink current.

Digital circuit characteristics over the operating temperature and voltage range.

Parameter

CD Signal Input Range

MO Signal Input Range

AGC Gain Range

Filter Cut Off - fc

Filter fc Accuracy

Max. Programmable Boost

3dB - no boost

fc=22.5 MHz

at Unboosted fc

3T to 8T pattern

Max. Boost

p-p differential

p-p single

2.3

4.0

-10

-1

1.5

3.3

Test Conditions

p-p differential

Min.

8.5

22.5

+10

Typ.

Max.

600

300

Units

V/V

MHz

Boost Level Accuracy

Filter Output Voltage

- DIFF

- NORM

AGC Gain Control

Active Region

The level of high frequency boost when applied (BOOST=HI) may be calculated from the following formula.

Fbst = 20*log

where :

[

(6.18*BOOSTSET - 1.38*VCCFILT)

]

(VCCFILT - 1.4*BOOSTSET)

BOOSTSET = Boost level control voltage (pin 50)

VCCFILT = Filter V

supply (pin 56) (5V nom.)

Note :

BOOSTSET must be related to VCCFILT and that the above formula holds for BOOSTSET from 0.3VCCFILT

to 0.5 VCCFILT. With BOOSTSET below 0.3 VCCFILT the boost level is zero, and with BOOSTSET above 0.5

VCCFILT the boost level is maximum.

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