PCA9306DC-G datasheet, PDF - EEWORLD Datasheet

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PCA9306DC-G: DescriptionIC SPECIALTY INTERFACE CIRCUIT, PDSO8, 2.30 MM, GREEN, PLASTIC, MO-187, SOT765-1, VSSOP-8, Interface IC:Other; CategoryAnalog mixed-signal IC Drivers and interfaces; File Size123KB，21 Pages; ManufacturerNXP; Websitehttps://www.nxp.com; Environmental Compliance

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PCA9306DC-G Overview

IC SPECIALTY INTERFACE CIRCUIT, PDSO8, 2.30 MM, GREEN, PLASTIC, MO-187, SOT765-1, VSSOP-8, Interface IC:Other

PCA9306DC-G Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Maker	NXP
Parts packaging code	TSSOP
package instruction	VSSOP, TSSOP8,.12,20
Contacts	8
Reach Compliance Code	unknown
Interface integrated circuit type	INTERFACE CIRCUIT
JESD-30 code	R-PDSO-G8
JESD-609 code	e4
length	2.3 mm
Humidity sensitivity level	1
Number of functions	1
Number of terminals	8
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Package body material	PLASTIC/EPOXY
encapsulated code	VSSOP
Encapsulate equivalent code	TSSOP8,.12,20
Package shape	RECTANGULAR
Package form	SMALL OUTLINE, VERY THIN PROFILE, SHRINK PITCH
Peak Reflow Temperature (Celsius)	260
Certification status	Not Qualified
Maximum seat height	1 mm
Maximum supply voltage	3.6 V
Minimum supply voltage	1.1 V
Nominal supply voltage	1.8 V
Supply voltage 1-max	5.5 V
Mains voltage 1-minute	2.3 V
Supply voltage1-Nom	3.3 V
surface mount	YES
Temperature level	INDUSTRIAL
Terminal surface	Nickel/Palladium/Gold (Ni/Pd/Au)
Terminal form	GULL WING
Terminal pitch	0.5 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	30
width	2 mm

PCA9306DC-G Preview

PCA9306

Dual bidirectional I

C-bus and SMBus voltage-level translator

Rev. 01 — 20 October 2006

Product data sheet

1. General description

The PCA9306 is a dual bidirectional I

C-bus and SMBus voltage-level translator with an

enable (EN) input, and is operational from 1.1 V to 3.6 V (V

ref(1)

) and 2.3 V to 5.5 V

bias(ref)(2)

The PCA9306 allows bidirectional voltage translations between 1.2 V and 5 V without the

use of a direction pin. The low ON-state resistance (R

) of the switch allows connections

to be made with minimal propagation delay. When EN is HIGH, the translator switch is on,

and the SCL1 and SDA1 I/O are connected to the SCL2 and SDA2 I/O, respectively,

allowing bidirectional data ﬂow between ports. When EN is LOW, the translator switch is

off, and a high-impedance state exists between ports.

In I

C-bus applications, the bus capacitance limit of 400 pF restricts the number of devices

and bus length. Using the PCA9306 enables the system designer to isolate two halves of

a bus, thus more I

C-bus devices or longer trace length can be accommodated by using

the enable pin. The PCA9306 is not a bus buffer like the PCA9509 or PCA9517 that

provides level translation and physically isolates the capacitance to either side of the bus

even when both sides are connected.

The PCA9306 can also be used to run two buses, one at 400 kHz operating frequency

and the other at 100 kHz operating frequency. If the two buses are operating at different

frequencies, the 100 kHz bus must be isolated when the 400 kHz operation of the other

bus is required. If the master is running at 400 kHz, the maximum system operating

frequency may be less than 400 kHz because of the delays added by the translator.

As with the standard I

C-bus system, pull-up resistors are required to provide the logic

HIGH levels on the translator’s bus. The PCA9306 has a standard open-collector

conﬁguration of the I

C-bus. The size of these pull-up resistors depends on the system,

but each side of the translator must have a pull-up resistor. The device is designed to work

with Standard-mode, Fast-mode and Fast mode Plus I

C-bus devices in addition to

SMBus devices.

When the SDA1 or SDA2 port is LOW, the clamp is in the ON-state and a low resistance

connection exists between the SDA1 and SDA2 ports. Assuming the higher voltage is on

the SDA2 port when the SDA2 port is HIGH, the voltage on the SDA1 port is limited to the

voltage set by VREF1. When the SDA1 port is HIGH, the SDA2 port is pulled to the drain

pull-up supply voltage (V

pu(D)

) by the pull-up resistors. This functionality allows a seamless

translation between higher and lower voltages selected by the user without the need for

directional control. The SCL1/SCL2 channel also functions as the SDA1/SDA2 channel.

NXP Semiconductors

PCA9306

Dual bidirectional I

C-bus and SMBus voltage-level translator

All channels have the same electrical characteristics and there is minimal deviation from

one output to another in voltage or propagation delay. This is a beneﬁt over discrete

transistor voltage translation solutions, since the fabrication of the switch is symmetrical.

The translator provides excellent ESD protection to lower voltage devices, and at the

same time protects less ESD-resistant devices.

2. Features

2-bit bidirectional translator for SDA and SCL lines in mixed-mode I

C-bus applications

Standard-mode, Fast-mode, and Fast-mode Plus I

C-bus and SMBus compatible

Less than 1.5 ns maximum propagation delay to accommodate Standard mode and

Fast mode I

C-bus devices and multiple masters

Allows voltage level translation between:

1.0 V V

ref(1)

and 1.8 V, 2.5 V, 3.3 V or 5 V V

bias(ref)(2)

1.2 V V

ref(1)

and 2.5 V, 3.3 V or 5 V V

bias(ref)(2)

1.8 V V

ref(1)

and 3.3 V or 5 V V

bias(ref)(2)

2.5 V V

ref(1)

and 5 V V

bias(ref)(2)

3.3 V V

ref(1)

and 5 V V

bias(ref)(2)

Provides bidirectional voltage translation with no direction pin

Low 3.5

Ω

ON-state connection between input and output ports provides less signal

distortion

Open-drain I

C-bus I/O ports (SCL1, SDA1, SCL2 and SDA2)

5 V tolerant I

C-bus I/O ports to support mixed-mode signal operation

High-impedance SCL1, SDA1, SCL2 and SDA2 pins for EN = LOW

Lock-up free operation for isolation when EN = LOW

Flow through pinout for ease of printed-circuit board trace routing

ESD protection exceeds 2000 V HBM per JESD22-A114, 200 V MM per

JESD22-A115, and 1000 V CDM per JESD22-C101

Packages offered: SO8, TSSOP8, VSSOP8, XQFN8

PCA9306_1

Product data sheet

Rev. 01 — 20 October 2006

2 of 21

NXP Semiconductors

PCA9306

Dual bidirectional I

C-bus and SMBus voltage-level translator

3. Ordering information

Table 1.

Ordering information

amb

−

C to +85

Type number

PCA9306D

PCA9306DP

PCA9306DC

PCA9306DP1

[2]

PCA9306DC1

[3]

PCA9306GM

Topside

mark

PCA9306

306P

306C

306T

306U

P06

Package

Name

SO8

TSSOP8

[1]

VSSOP8

TSSOP8

VSSOP8

XQFN8

Description

plastic small outline package; 8 leads; body width 3.9 mm

plastic thin shrink small outline package; 8 leads;

body width 3 mm

plastic very thin shrink small outline package; 8 leads;

body width 2.3 mm

plastic thin shrink small outline package; 8 leads;

body width 3 mm; lead length 0.5 mm

plastic very thin shrink small outline package; 8 leads;

body width 2.3 mm

plastic extremely thin quad ﬂat package; no leads;

8 terminals; body 1.6

1.6

0.5 mm

Version

SOT96-1

SOT505-1

SOT765-1

SOT505-2

SOT765-1

SOT902-1

[1]

[2]

[3]

Also known as MSOP8.

Same footprint and pinout as the Texas Instruments PCA9306DCT.

Same footprint and pinout as the Texas Instruments PCA9306DCU.

4. Functional diagram

VREF1

VREF2

SCL2

PCA9306

SCL1

SDA1

SDA2

GND

002aab844

Fig 1. Logic diagram of PCA9306 (positive logic)

PCA9306_1

Product data sheet

Rev. 01 — 20 October 2006

3 of 21

NXP Semiconductors

PCA9306

Dual bidirectional I

C-bus and SMBus voltage-level translator

5. Pinning information

5.1 Pinning

GND

VREF1

SCL1

SDA1

002aab842

VREF2

SCL2

SDA2

GND

VREF1

SCL1

SDA1

002aac373

VREF2

SCL2

SDA2

PCA9306DP1

PCA9306DP

Fig 2. Pin conﬁguration for TSSOP8

Fig 3. Pin conﬁguration for TSSOP8

(MSOP8)

VREF1

SCL1

SDA1

GND

002aac374

VREF2

SCL2

SDA2

GND

VREF1

SCL1

SDA1

002aab843

VREF2

SCL2

SDA2

PCA9306DC

PCA9306DC1

Fig 4. Pin conﬁguration for VSSOP8 (DC)

Fig 5. Pin conﬁguration for VSSOP8 (DC1)

terminal 1

index area

GND

VREF2

PCA9306GM

VREF1

GND

VREF1

SCL1

SDA1

VREF2

SCL2

SDA2

SCL1

SDA2

SCL2

PCA9306D

SDA1

002aac372

002aac375

Transparent top view

Fig 6. Pin conﬁguration for SO8

Fig 7. Pin conﬁguration for XQFN8

PCA9306_1

Product data sheet

Rev. 01 — 20 October 2006

4 of 21

NXP Semiconductors

PCA9306

Dual bidirectional I

C-bus and SMBus voltage-level translator

5.2 Pin description

Table 2.

Symbol

Pin description

SO8,

VSSOP8 (DC)

TSSOP8 (MSOP8),

TSSOP8,

VSSOP8 (DC1),

XQFN8

GND

VREF1

SCL1

SDA1

SDA2

SCL2

VREF2

ground (0 V)

low-voltage side reference supply voltage for

SCL1 and SDA1

serial clock, low-voltage side; connect to

VREF1 through a pull-up resistor

serial data, low-voltage side; connect to VREF1

through a pull-up resistor

serial data, high-voltage side; connect to

VREF2 through a pull-up resistor

serial clock, high-voltage side; connect to

VREF2 through a pull-up resistor

high-voltage side reference supply voltage for

SCL2 and SDA2

switch enable input; connect to VREF2 and

pull-up through a high resistor

Description

6. Functional description

Refer to

Figure 1 “Logic diagram of PCA9306 (positive logic)”.

6.1 Function table

Table 3.

Function selection (example)

H = HIGH level; L = LOW level.

Input EN

[1]

Function

SCL1 = SCL2; SDA1 = SDA2

disconnect

EN is controlled by the V

bias(ref)(2)

logic levels and should be at least 1 V higher than V

ref(1)

for best translator

operation.

PCA9306_1

Product data sheet

Rev. 01 — 20 October 2006

5 of 21

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PCA9306DC-G Related Products

	PCA9306DC-G	PCA9306D-T
Description	IC SPECIALTY INTERFACE CIRCUIT, PDSO8, 2.30 MM, GREEN, PLASTIC, MO-187, SOT765-1, VSSOP-8, Interface IC:Other	IC SPECIALTY INTERFACE CIRCUIT, PDSO8, 3.90 MM, PLASTIC, MS-012, SOT96-1, SOP-8, Interface IC:Other
Is it Rohs certified?	conform to	conform to
Maker	NXP	NXP
Parts packaging code	TSSOP	SOIC
package instruction	VSSOP, TSSOP8,.12,20	3.90 MM, PLASTIC, MS-012, SOT96-1, SOP-8
Contacts	8	8
Reach Compliance Code	unknown	unknown
Interface integrated circuit type	INTERFACE CIRCUIT	INTERFACE CIRCUIT
JESD-30 code	R-PDSO-G8	R-PDSO-G8
JESD-609 code	e4	e4
length	2.3 mm	4.9 mm
Humidity sensitivity level	1	1
Number of functions	1	1
Number of terminals	8	8
Maximum operating temperature	85 °C	85 °C
Minimum operating temperature	-40 °C	-40 °C
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	VSSOP	SOP
Encapsulate equivalent code	TSSOP8,.12,20	SOP8,.25
Package shape	RECTANGULAR	RECTANGULAR
Package form	SMALL OUTLINE, VERY THIN PROFILE, SHRINK PITCH	SMALL OUTLINE
Peak Reflow Temperature (Celsius)	260	260
Certification status	Not Qualified	Not Qualified
Maximum seat height	1 mm	1.75 mm
Maximum supply voltage	3.6 V	3.6 V
Minimum supply voltage	1.1 V	1.1 V
Nominal supply voltage	1.8 V	1.8 V
Supply voltage 1-max	5.5 V	5.5 V
Mains voltage 1-minute	2.3 V	2.3 V
Supply voltage1-Nom	3.3 V	3.3 V
surface mount	YES	YES
Temperature level	INDUSTRIAL	INDUSTRIAL
Terminal surface	Nickel/Palladium/Gold (Ni/Pd/Au)	NICKEL PALLADIUM GOLD
Terminal form	GULL WING	GULL WING
Terminal pitch	0.5 mm	1.27 mm
Terminal location	DUAL	DUAL
Maximum time at peak reflow temperature	30	30
width	2 mm	3.9 mm

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