MOTOROLA
Freescale Semiconductor, Inc.
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by MCM69R737A/D
SEMICONDUCTOR TECHNICAL DATA
Advance Information
4M Late Write LVTTL
MCM69R737A
MCM69R819A
Freescale Semiconductor, Inc...
The MCM69R737A/819A is a 4 megabit synchronous late write fast static RAM
designed to provide high performance in secondary cache and ATM switch,
Telecom, and other high speed memory applications. The MCM69R819A
organized as 256K words by 18 bits, and the MCM69R737A organized as 128K
words by 36 bits wide are fabricated in Motorola’s high performance silicon gate
BiCMOS technology.
The differential CK clock inputs control the timing of read/write operations of
R,
the RAM. At the rising edge of the CK clock all addresses, write enables, and
TO
synchronous selects are registered. An internal buffer and special logic enable
UC
the memory to accept write data on the rising edge of the CK clock a cycle after
ND
address and control signals. Read data is driven on the rising edge of the CK
CO
clock also.
I
M
The RAM uses LVTTL 3.3 V inputs and outputs.
SE
The synchronous write and byte enables allow writing to individual bytes or the
LE
entire word.
Byte Write Control
SC
Single 3.3 V + 10%, – 5% Operation
EE
LVTTL 3.3 V I/O (VDDQ)
FR
Register to Register Synchronous Operation
BY
Asynchronous Output Enable
ED
Compatible
Boundary Scan (JTAG) IEEE
IV
1149.1
Differential Clock Inputs
H
RC
Optional x 18 or x 36 organization
A
MCM69R737A/819A–5 = 5 ns
MCM69R737A/819A–6 = 6 ns
MCM69R737A/819A–7 = 7 ns
MCM69R737A/819A–8 = 8 ns
•
Sleep Mode Operation (ZZ Pin)
•
119 Bump, 50 mil (1.27 mm) Pitch, 14 mm x 22 mm Plastic Ball Grid Array
(PBGA) Package
•
•
•
•
•
•
•
•
•
I
C.
N
ZP PACKAGE
PBGA
CASE 999–01
A
This document contains information on a new product. Specifications and information herein are subject to change without notice.
REV 1
8/13/97
©
Motorola, Inc. 1997
MOTOROLA FAST SRAM
For More Information On This Product,
Go to: www.freescale.com
MCM69R737A•MCM69R819A
1
Freescale Semiconductor, Inc.
FUNCTIONAL BLOCK DIAGRAM
DATA IN
REGISTER
DQ
DATA OUT
REGISTER
SA
ADDRESS
REGISTERS
MEMORY
ARRAY
SW
SBx
SW
REGISTERS
CONTROL
LOGIC
CK
G
Freescale Semiconductor, Inc...
SS
SS
REGISTERS
MCM69R737A
Y
B
1
A
B
C
D
E
DQc
F
G
DQc
H
J
K
L
DQd
M
VDDQ DQd
N
P
R
T
U
DQd
DQd
NC
NC
DQd
DQd
SA
NC
VSS
VSS
VSS
VSS
SA
TDI
SW
SA
SA
VDD
SA
TCK
VSS
VSS
VSS
VDD
SA
TDO
DQd
SBd
CK
SBa
DQc
DQc
DQc
SBc
VSS
NC
VSS
NC
NC
VDD
CK
SBb
VSS
NC
VSS
DQc
VSS
VSS
SS
G
VSS
VSS
VDDQ
NC
NC
DQc
2
SA
3
SA
E
E
PIN ASSIGNMENTS
FR
TOP VIEW
MCM69R819A
7
VDDQ
NC
NC
DQb
DQb
F
G
A
B
C
D
E
1
VDDQ
NC
NC
DQb
NC
VDDQ
NC
H
J
K
L
DQb
2
SA
NC
SA
NC
DQb
NC
DQb
NC
3
SA
SA
SA
VSS
VSS
VSS
SBb
VSS
NC
VSS
VSS
VSS
VSS
VSS
VSS
SA
TDI
4
NC
NC
VDD
NC
SS
G
NC
NC
VDD
CK
CK
SW
SA
SA
VDD
NC
TCK
5
SA
SA
SA
VSS
VSS
VSS
VSS
VSS
NC
VSS
SBa
VSS
VSS
VSS
VDD
SA
TDO
6
SA
NC
SA
DQa
NC
7
VDDQ
NC
NC
NC
DQa
LE
CA
S
S
CO
I
M
E
,I
OR
CT
DU
N
C.
N
CH
NC
AR
SA NC
NC
SA
DQc
SA
VSS
NC
5
ED
V
I
4
6
SA
NC
SA
DQb
DQb
SA
SA
SA
VSS
VDD
VDDQ DQc
DQb VDDQ
DQb
DQb
DQb
DQb
DQa VDDQ
NC
DQa
DQa
NC
VDDQ VDD
DQd
DQd
VDD VDDQ
DQa
DQa
DQa
DQa
VDDQ VDD
NC
DQb
DQb
NC
VDD VDDQ
NC
DQa
DQa
NC
M
DQa VDDQ
DQa
DQa
SA
NC
DQa
DQa
NC
ZZ
N
P
R
T
NC
U
SA
SA
ZZ
VDDQ TMS
NC VDDQ
VDDQ DQb
DQb
NC
NC
NC
DQb
SA
NC VDDQ
DQa
NC
SA
NC
DQa
NC
VDDQ TMS
NC VDDQ
MCM69R737A•MCM69R819A
2
For More Information On This Product,
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MOTOROLA FAST SRAM
Freescale Semiconductor, Inc.
MCM69R737A PIN DESCRIPTIONS
PBGA Pin Locations
4K
4L
(a) 6K, 7K, 6L, 7L, 6M, 6N, 7N, 6P, 7P
(b) 6D, 7D, 6E, 7E, 6F, 6G, 7G, 6H, 7H
(c) 1D, 2D, 1E, 2E, 2F, 1G, 2G, 1H, 2H
(d) 1K, 2K, 1L, 2L, 2M, 1N, 2N, 1P, 2P
4F
2A, 3A, 5A, 6A, 3B, 5B, 2C, 3C,
5C, 6C, 4N, 4P, 2R, 6R, 3T, 4T, 5T
5L, 5G, 3G, 3L
(a), (b), (c), (d)
4E
Symbol
CK
CK
DQx
Type
Input
Input
I/O
Description
Address, data in and control input register clock. Active high.
Address, data in and control input register clock. Active low.
Synchronous Data I/O.
G
SA
SBx
Input
Input
Input
Output Enable: Asynchronous pin, active low.
Synchronous Address Inputs: Registered on the rising clock edge.
Synchronous Byte Write Enable: Enables writes to byte x in
conjunction with the SW input. Has no effect on read cycles, active
low.
Freescale Semiconductor, Inc...
4M
4U
3U
5U
2U
7T
4C, 2J, 4J, 6J, 4R, 5R
1A, 7A, 1F, 7F, 1J, 7J, 1M, 7M, 1U, 7U
3D, 5D, 3E, 5E, 3F, 5F, 3H, 5H,
3K, 5K, 3M, 5M, 3N, 5N, 3P, 5P, 3R
4A, 1B, 2B, 4B, 6B, 7B, 1C, 7C, 4D, 4G,
4H, 3J, 5J, 1R, 7R, 1T, 2T, 6T, 6U
CH
AR
ED
IV
,I
OR
on the rising clock edge, active
SS
Input
Synchronous Chip Enable: Registered
CT
low.
DU
N
SW
Input
Synchronous Write: Registered on the rising clock edge, active low.
O
bytes.
Writes all enabled
IC
M
TCK
Input
Test Clock (JTAG).
SE
TDI
Input
Test
LE
Data In (JTAG).
TDO
Output Test Data Out (JTAG).
CA
S
E
Input Test Mode Select (JTAG).
TMS
RE
Input Enables sleep mode, active high.
ZZ
F
Y
Supply Core Power Supply.
B
VDD
VDDQ
VSS
NC
Supply
Supply
—
Output Power Supply: provides operating power for output buffers.
Ground.
No Connection: There is no connection to the chip.
Note: 3J and 5J are tied common.
C.
N
MOTOROLA FAST SRAM
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MCM69R737A•MCM69R819A
3
Freescale Semiconductor, Inc.
MCM69R819A PIN DESCRIPTIONS
PBGA Pin Locations
4K
4L
(a) 6D, 7E, 6F, 7G, 6H, 7K, 6L, 6N, 7P
(b) 1D, 2E, 2G, 1H, 2K, 1L, 2M, 1N, 2P
4F
2A, 3A, 5A, 6A, 3B, 5B, 2C, 3C, 5C,
6C, 4N, 4P, 2R, 6R, 2T, 3T, 5T, 6T
5L, 3G
(a), (b)
4E
4M
Symbol
CK
CK
DQx
G
SA
SBx
Type
Input
Input
I/O
Input
Input
Input
Description
Address, data in and control input register clock. Active high.
Address, data in and control input register clock. Active low.
Synchronous Data I/O.
Output Enable: Asynchronous pin, active low.
Synchronous Address Inputs: Registered on the rising clock edge.
Synchronous Byte Write Enable: Enables writes to byte x in
conjunction with the SW input. Has no effect on read cycles, active
low.
Freescale Semiconductor, Inc...
4U
3U
5U
2U
7T
4C, 2J, 4J, 6J, 4R, 5R
1A, 7A, 1F, 7F, 1J, 7J, 1M, 7M, 1U, 7U
3D, 5D, 3E, 5E, 3F, 5F, 5G, 3H, 5H,
3K, 5K, 3L, 3M, 5M, 3N, 5N, 3P, 5P, 3R
4A, 1B, 2B, 4B, 6B, 7B, 1C, 7C,
2D, 4D, 7D, 1E, 6E, 2F, 1G, 4G, 6G,
2H, 4H, 7H, 3J, 5J, 1K, 6K, 2L, 7L, 6M, 2N,
7N, 1P, 6P, 1R, 7R, 1T, 4T, 6U
CH
AR
ED
IV
,I
OR
CT
SW
Input
Synchronous Write: Registered on the rising clock edge, active low.
Writes all enabled bytes.
DU
ON
TCK
Input
Test Clock (JTAG).
IC
TDI
Input
Test Data
M
(JTAG).
In
SE
TDO
Output Test Data Out (JTAG).
LE
Mode Select (JTAG).
TMS
Input
A
Test
SC
Enables sleep mode, active high.
ZZ
Input
EE
VDD
R
Supply Core Power Supply.
F
VDDQ
Supply Output Power Supply: provides operating power for output buffers.
BY
SS
Input
VSS
NC
Supply
—
Ground.
No Connection: There is no connection to the chip.
Note: 3J and 5J are tied common.
Synchronous Chip Enable: Registered on the rising clock edge, active
low.
C.
N
MCM69R737A•MCM69R819A
4
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Go to: www.freescale.com
MOTOROLA FAST SRAM
Freescale Semiconductor, Inc.
ABSOLUTE MAXIMUM RATINGS
(Voltages Referenced to VSS, See Note 1)
Rating
Core Supply Voltage
Output Supply Voltage
Voltage On Any Pin
Input Current (per I/O)
Output Current (per I/O)
Power Dissipation (See Note 2)
Operating Temperature
Temperature Under Bias
Storage Temperature
Symbol
VDD
VDDQ
Vin
Iin
Iout
PD
TA
Tbias
Tstg
Value
– 0.5 to + 4.6
– 0.5 to VDD + 0.5
– 0.5 to VDD + 0.5
±
50
±
70
—
0 to + 70
–10 to + 85
– 55 to + 125
Unit
V
V
V
mA
mA
W
°C
°C
°C
This device contains circuitry to protect the
inputs against damage due to high static volt-
ages or electric fields; however, it is advised
that normal precautions be taken to avoid
application of any voltage higher than maxi-
mum rated voltages to this high–impedance
circuit.
This BiCMOS memory circuit has been
designed to meet the dc and ac specifications
shown in the tables, after thermal equilibrium
has been established.
This device contains circuitry that will ensure
the output devices are in High–Z at power up.
Freescale Semiconductor, Inc...
NOTES:
1. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are
exceeded. Functional operation should be restricted to RECOMMENDED OPER-
ATING CONDITIONS. Exposure to higher than recommended voltages for extended
periods of time could affect device reliability.
2. Power dissipation capability will be dependent upon package characteristics and use
environment. See enclosed thermal impedance data.
PBGA PACKAGE THERMAL CHARACTERISTICS
Rating
Junction to Ambient (Still Air)
Junction to Ambient (@200 ft/min)
Junction to Ambient (@200 ft/min)
Junction to Board (Bottom)
Junction to Case (Top)
NOTES:
1. Junction temperature is a function of on–chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient
temperature, air flow, power dissipation of other components on the board, and board thermal resistance.
2. Per SEMI G38–87.
3. Indicates the average thermal resistance between the die and the printed circuit board.
4. Indicates the average thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC–883
Method 1012.1).
CH
AR
ED
IV
BY
EE
FR
LE
CA
S
S
CO
I
M
E
,I
OR
CT
DU
N
C.
N
Symbol
R
θJA
R
θJA
R
θJA
R
θJB
R
θJC
Max
53
38
22
14
5
Unit
°C/W
°C/W
°C/W
°C/W
°C/W
Notes
1, 2
1, 2
Single Layer Board
Four Layer Board
3
4
CLOCK TRUTH TABLE
K
L–H
L–H
L–H
L–H
L–H
L–H
L–H
L–H
L–H
X
ZZ
L
L
L
L
L
L
L
L
L
H
SS
L
L
L
L
L
L
L
H
H
X
SW
H
L
L
L
L
L
L
H
L
X
SBa
X
L
H
H
H
L
H
X
X
X
SBb
X
H
L
H
H
L
H
X
X
X
SBc
X
H
H
L
H
L
H
X
X
X
SBd
X
H
H
H
L
L
H
X
X
X
DQ (n)
X
High–Z
High–Z
High–Z
High–Z
High–Z
High–Z
X
High–Z
High–Z
DQ (n+1)
Dout 0–35
Din 0–8
Din 9–17
Din 18–26
Din 27–35
Din 0–35
High–Z
High–Z
High–Z
High–Z
Mode
Read Cycle All Bytes
Write Cycle 1st Byte
Write Cycle 2nd Byte
Write Cycle 3rd Byte
Write Cycle 4th Byte
Write Cycle All Bytes
Abort Write Cycle
Deselect Cycle
Deselect Cycle
Sleep Mode
MOTOROLA FAST SRAM
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MCM69R737A•MCM69R819A
5
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