ZBT SRAM, 256KX18, 3.2ns, CMOS, PBGA119, 14 X 22 MM, PLASTIC, MS-028AA, BGA-119
IDT71V2558S200BG Parametric
Parameter Name
Attribute value
Is it Rohs certified?
incompatible
Maker
IDT (Integrated Device Technology)
Parts packaging code
BGA
package instruction
14 X 22 MM, PLASTIC, MS-028AA, BGA-119
Contacts
119
Reach Compliance Code
not_compliant
ECCN code
3A991.B.2.A
Maximum access time
3.2 ns
Other features
PIPELINED ARCHITECTURE
Maximum clock frequency (fCLK)
200 MHz
I/O type
COMMON
JESD-30 code
R-PBGA-B119
JESD-609 code
e0
length
22 mm
memory density
4718592 bit
Memory IC Type
ZBT SRAM
memory width
18
Humidity sensitivity level
3
Number of functions
1
Number of terminals
119
word count
262144 words
character code
256000
Operating mode
SYNCHRONOUS
Maximum operating temperature
70 °C
Minimum operating temperature
organize
256KX18
Output characteristics
3-STATE
Package body material
PLASTIC/EPOXY
encapsulated code
BGA
Encapsulate equivalent code
BGA119,7X17,50
Package shape
RECTANGULAR
Package form
GRID ARRAY
Parallel/Serial
PARALLEL
Peak Reflow Temperature (Celsius)
NOT SPECIFIED
power supply
2.5,3.3 V
Certification status
Not Qualified
Maximum seat height
2.36 mm
Maximum standby current
0.04 A
Minimum standby current
3.14 V
Maximum slew rate
0.4 mA
Maximum supply voltage (Vsup)
3.465 V
Minimum supply voltage (Vsup)
3.135 V
Nominal supply voltage (Vsup)
3.3 V
surface mount
YES
technology
CMOS
Temperature level
COMMERCIAL
Terminal surface
Tin/Lead (Sn63Pb37)
Terminal form
BALL
Terminal pitch
1.27 mm
Terminal location
BOTTOM
Maximum time at peak reflow temperature
NOT SPECIFIED
width
14 mm
IDT71V2558S200BG Preview
128K x 36, 256K x 18
3.3V Synchronous ZBT™ SRAMs
2.5V I/O, Burst Counter
Pipelined Outputs
x
x
IDT71V2556
IDT71V2558
Features
128K x 36, 256K x 18 memory configurations
Supports high performance system speed - 200 MHz
(3.2 ns Clock-to-Data Access)
ZBT
TM
Feature - No dead cycles between write and read
cycles
Internally synchronized output buffer enable eliminates the
need to control
OE
Single R/W (READ/WRITE) control pin
W
Positive clock-edge triggered address, data, and control
signal registers for fully pipelined applications
4-word burst capability (interleaved or linear)
Individual byte write (BW
1
-
BW
4
) control (May tie active)
Three chip enables for simple depth expansion
3.3V power supply (±5%)
2.5V I/O Supply (V
DDQ)
Packaged in a JEDEC standard 100-pin plastic thin quad
flatpack (TQFP), 119 ball grid array (BGA) and 165 fine pitch
ball grid array (fBGA)
cycle, and two cycles later the associated data cycle occurs, be it read
or write.
The IDT71V2556/58 contain data I/O, address and control signal
registers. Output enable is the only asynchronous signal and can be used
to disable the outputs at any given time.
A Clock Enable (CEN) pin allows operation of the IDT71V2556/58 to
be suspended as long as necessary. All synchronous inputs are ignored
when (CEN) is high and the internal device registers will hold their previous
values.
There are three chip enable pins (CE
1
, CE
2
,
CE
2
) that allow the user
to deselect the device when desired. If any one of these three are not
asserted when ADV/LD is low, no new memory operation can be initiated.
However, any pending data transfers (reads or writes) will be completed.
The data bus will tri-state two cycles after chip is deselected or a write is
initiated.
The IDT71V2556/58 has an on-chip burst counter. In the burst mode,
the IDT71V2556/58 can provide four cycles of data for a single address
presented to the SRAM. The order of the burst sequence is defined by the
LBO
input pin. The
LBO
pin selects between linear and interleaved burst
sequence. The ADV/LD signal is used to load a new external address
(ADV/LD = LOW) or increment the internal burst counter (ADV/LD =
HIGH).
The IDT71V2556/58 SRAMs utilize IDT's latest high-performance
CMOS process and are packaged in a JEDEC standard 14mm x 20mm
100-pin thin plastic quad flatpack (TQFP) as well as a 119 ball grid array
(BGA) and a 165 fine pitch ball grid array (fBGA).
x
x
x
x
x
x
x
x
x
x
Description
The IDT71V2556/58 are 3.3V high-speed 4,718,592-bit (4.5 Mega-
bit) synchronous SRAMS. They are designed to eliminate dead bus cycles
when turning the bus around between reads and writes, or writes and
reads. Thus, they have been given the name ZBT
TM
, or Zero Bus
Turnaround.
Address and control signals are applied to the SRAM during one clock
Pin Description Summary
A
0
-A
17
CE
1
, CE
2
,
CE
2
OE
R/W
CEN
BW
1
,
BW
2
,
BW
3
,
BW
4
CLK
ADV/LD
LBO
I/O
0
-I/O
31
, I/O
P1
-I/O
P4
V
DD
, V
DDQ
V
SS
Address Inputs
Chip Enables
Output Enable
Read/Write Signal
Clock Enable
Individual Byte Write Selects
Clock
Advance burst address / Load new address
Linear / Interleaved Burst Order
Data Input / Output
Core Power, I/O Power
Ground
Input
Input
Input
Input
Input
Input
Input
Input
Input
I/O
Supply
Supply
Synchronous
Synchronous
Asynchronous
Synchronous
Synchronous
Synchronous
N/A
Synchronous
Static
Synchronous
Static
Static
4875 tbl 01
ZBT and ZeroBus Turnaround are trademarks of Integrated Device Technology, Inc. and the architecture is supported by Micron Technology and Motorola Inc.
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