BUK9Y53-100B
N-channel TrenchMOS logic level FET
Rev. 01 — 30 August 2007
Product data sheet
1. Product profile
1.1 General description
N-channel enhancement mode power Field-Effect Transistor (FET) in a plastic package
using NXP High-Performance Automotive (HPA) TrenchMOS technology.
1.2 Features
I
Very low on-state resistance
I
175
°C
rated
I
Q101 compliant
I
Logic level compatible
1.3 Applications
I
Automotive systems
I
Motors, lamps and solenoids
I
General purpose power switching
I
12 V, 24 V and 42 V loads
1.4 Quick reference data
I
E
DS(AL)S
≤
85 mJ
I
I
D
≤
23 A
I
R
DSon
= 45 mΩ (typ)
I
P
tot
≤
75 W
2. Pinning information
Table 1.
Pin
4
mb
Pinning
Description
gate (G)
mounting base; connected to drain (D)
G
Simplified outline
mb
Symbol
D
1, 2, 3 source (S)
1 2 3 4
mbl798
S1 S2 S3
SOT669 (LFPAK)
NXP Semiconductors
BUK9Y53-100B
N-channel TrenchMOS logic level FET
3. Ordering information
Table 2.
Ordering information
Package
Name
BUK9Y53-100B
LFPAK
Description
plastic single-ended surface-mounted package (LFPAK); 4 leads
Version
SOT669
Type number
4. Limiting values
Table 3.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
V
DS
V
DGR
V
GS
I
D
I
DM
P
tot
T
stg
T
j
I
DR
I
DRM
E
DS(AL)S
Parameter
drain-source voltage
drain-gate voltage (DC)
gate-source voltage
drain current
peak drain current
total power dissipation
storage temperature
junction temperature
reverse drain current
peak reverse drain current
non-repetitive drain-source avalanche
energy
repetitive drain-source avalanche
energy
T
mb
= 25
°C
T
mb
= 25
°C;
pulsed; t
p
≤
10
µs
unclamped inductive load; I
D
= 23 A;
V
DS
≤
100 V; V
GS
= 5 V; R
GS
= 50
Ω;
starting at
T
j
= 25
°C
T
mb
= 25
°C;
V
GS
= 5 V; see
Figure 2
and
3
T
mb
= 100
°C;
V
GS
= 5 V; see
Figure 2
T
mb
= 25
°C;
pulsed; t
p
≤
10
µs;
see
Figure 3
T
mb
= 25
°C;
see
Figure 1
R
GS
= 20 kΩ
Conditions
Min Max
-
-
-
-
-
-
-
100
100
±15
23
16
94
75
Unit
V
V
V
A
A
A
W
−55
+175
°C
−55
+175
°C
-
-
-
23
94
85
A
A
mJ
Source-drain diode
Avalanche ruggedness
E
DS(AL)R
-
[1]
-
[1]
Conditions:
a) Maximum value not quoted. Repetitive rating defined in
Figure 16.
b) Single-pulse avalanche rating limited by T
j(max)
of 175
°C.
c) Repetitive avalanche rating limited by T
j(avg)
of 170
°C.
d) Refer to application note
AN10273
for further information.
BUK9Y53-100B_1
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 01 — 30 August 2007
2 of 12
NXP Semiconductors
BUK9Y53-100B
N-channel TrenchMOS logic level FET
120
P
der
(%)
80
003aab844
30
I
D
(A)
20
003aab225
40
10
0
0
50
100
150
T
mb
(°C)
200
0
0
50
100
150
T
mb
(°C)
200
P
tot
P
der
=
-----------------------
×
100
%
-
P
tot
(
25°C
)
Fig 1. Normalized total power dissipation as a
function of mounting base temperature
10
3
I
D
(A)
10
2
Limit R
DSon
= V
DS
/ I
D
V
GS
≥
5 V
Fig 2. Continuous drain current as a function of
mounting base temperature
003aab226
t
p
= 10
µs
10
100
µs
1
DC
1 ms
10 ms
100 ms
10
−1
1
10
10
2
V
DS
(V)
10
3
T
mb
= 25
°C;
I
DM
is single pulse.
Fig 3. Safe operating area; continuous and peak drain currents as a function of drain-source voltage
BUK9Y53-100B_1
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 01 — 30 August 2007
3 of 12
NXP Semiconductors
BUK9Y53-100B
N-channel TrenchMOS logic level FET
5. Thermal characteristics
Table 4:
Symbol
R
th(j-mb)
Thermal characteristics
Parameter
Conditions
Min
-
Typ
-
Max
2
Unit
K/W
thermal resistance from junction to mounting base see
Figure 4
1
Z
th(j−mb)
(K/W)
1
δ
= 0.5
0.2
0.1
10
−1
0.05
0.02
t
p
T
P
003aab219
δ
=
t
p
T
t
single pulse
10
−2
10
−6
10
−5
10
−4
10
−3
10
−2
10
−1
1
t
p
(s)
Fig 4. Transient thermal impedance from junction to mounting base as a function of pulse duration
BUK9Y53-100B_1
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 01 — 30 August 2007
4 of 12
NXP Semiconductors
BUK9Y53-100B
N-channel TrenchMOS logic level FET
6. Characteristics
Table 5:
Characteristics
T
j
= 25
°
C unless otherwise specified.
Symbol
V
(BR)DSS
Parameter
Conditions
Min
Typ
Max
Unit
Static characteristics
drain-source breakdown voltage I
D
= 0.25 mA; V
GS
= 0 V
T
j
= 25
°C
T
j
=
−55 °C
V
GS(th)
gate-source threshold voltage
I
D
= 1 mA; V
DS
= V
GS
; see
Figure 9
and
10
T
j
= 25
°C
T
j
= 175
°C
T
j
=
−55 °C
I
DSS
drain leakage current
V
DS
= 100 V; V
GS
= 0 V
T
j
= 25
°C
T
j
= 175
°C
I
GSS
R
DSon
gate leakage current
V
GS
=
±15
V; V
DS
= 0 V
T
j
= 25
°C
T
j
= 175
°C
V
GS
= 4.5 V; I
D
= 10 A
V
GS
= 10 V; I
D
= 10 A
Dynamic characteristics
Q
G(tot)
Q
GS
Q
GD
C
iss
C
oss
C
rss
t
d(on)
t
r
t
d(off)
t
f
V
SD
t
rr
Q
r
total gate charge
gate-source charge
gate-drain charge
input capacitance
output capacitance
reverse transfer capacitance
turn-on delay time
rise time
turn-off delay time
fall time
source-drain voltage
reverse recovery time
recovered charge
I
S
= 25 A; V
GS
= 0 V; see
Figure 15
I
S
= 20 A; dI
S
/dt =
−100
A/µs;
V
GS
=
0
V; V
R
= 30 V
V
DS
= 30 V; R
L
= 2.5
Ω;
V
GS
= 5 V; R
G
= 10
Ω
V
GS
= 0 V; V
DS
= 25 V; f = 1 MHz;
see
Figure 12
I
D
= 15 A; V
DS
= 80 V; V
GS
= 5 V;
see
Figure 14
-
-
-
-
-
-
-
-
-
-
-
-
-
18
4.1
8
1600
141
60
18
26
52
16
0.85
71
83
-
-
-
2130
170
82
-
-
-
-
1.2
-
-
nC
nC
nC
pF
pF
pF
ns
ns
ns
ns
V
ns
nC
drain-source on-state resistance V
GS
= 5 V; I
D
= 10 A; see
Figure 6
and
8
-
-
-
-
45
-
-
41
53
132
59
49
mΩ
mΩ
mΩ
mΩ
-
-
-
0.02
-
2
1
500
100
µA
µA
nA
1.1
0.5
-
1.5
-
-
2
-
2.3
V
V
V
100
89
-
-
-
-
V
V
Source-drain diode
BUK9Y53-100B_1
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 01 — 30 August 2007
5 of 12
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