GS2960A datasheet, PDF - EEWORLD Datasheet

Datasheet> All Categories > GS2960A

Preview

GS2960A: DescriptionAncillary data extraction; File Size7MB，99 Pages; ManufacturerGennum ( Semtech ); Websitehttp://www.gennum.com

Download Datasheet View All

GS2960A Overview

Ancillary data extraction

Preview

Download Datasheet

View All

GS2960A

3Gb/s, HD, SD SDI Receiver Complete with SMPTE Video Processing

Key Features

•

Operation at 2.97Gb/s, 2.97/1.001Gb/s, 1.485Gb/s,

1.485/1.001Gb/s and 270Mb/s

Supports SMPTE 425M (Level A and Level B), SMPTE

424M, SMPTE 292, SMPTE 259M-C and DVB-ASI

Integrated Reclocker

Integrated low phase noise VCO

Serial digital reclocked, or non-reclocked loop-through

output

Ancillary data extraction

Optional conversion from SMPTE 425M Level B to

Level A for 1080p 50/60 4:2:2 10-bit inputs

Parallel data bus selectable as either 20-bit or 10-bit

Comprehensive error detection and correction

features

Output H, V, F or CEA 861 Timing Signals

1.2V digital core power supply, 1.2V and 3.3V analog

power supplies, and selectable 1.8V or 3.3V I/O power

supply

GSPI Host Interface

Wide temperature range of -40ºC to +85ºC

Low power operation (typically 350 mW)

Small 11mm x 11mm 100-ball BGA package

Pb-free and RoHS compliant

HD-SDI

Link B

HD-SDI

Link A

Application: Dual Link (HD-SDI)

to Single Link (3G-SDI) Converter

HD-SDI

Deserializer

GS2960A

10-bit

FIFO

HV F/PCLK

3G-SDI

GS2962

HD-SDI

Deserializer

GS2960A

10-bit

FIFO

HV F/PCLK

HV F

GS4910

X TAL

Description

The GS2960A is a multi-rate SDI Receiver which includes

complete SMPTE processing, as per SMPTE 425M, 292 and

SMPTE 259M-C. The SMPTE processing features can be

bypassed to support signals with other coding schemes.

The device features an integrated Reclocker with an

internal VCO and a wide Input Jitter Tolerance (IJT) of

0.7UI.

A serial digital loop through output is provided, which can

be configured to output either reclocked or non-reclocked

serial digital data. The Serial Digital Output can be

connected to an external Cable Driver.

The device operates in one of four basic modes: SMPTE

mode, DVB-ASI mode, Data-Through mode or Standby

mode.

In SMPTE mode, the GS2960A performs SMPTE

de-scrambling and NRZI to NRZ decoding and word

alignment. Line-based CRC errors, line number errors, TRS

errors and ancillary data check sum errors can all be

detected. The GS2960A also provides ancillary data

extraction. The entire ancillary data packet is extracted,

and written to host-accessible registers. Other processing

functions include H:V:F timing extraction, Luma and

Chroma ancillary data indication, video standard

detection, and SMPTE 352M packet detection and

decoding. All of the processing features are optional and

may be enabled or disabled via the Host Interface.

1 of 99

•

Applications

Application: Single Link (3G-SDI)

to Dual Link (HD-SDI) Converter

10-bit

HD-SDI

GS2962

HV F/PCLK

Link A

3G-SDI

Gennum

Equalizer

GS2960A

HV F/PCLK

10-bit

GS2962

HD-SDI

Link B

GS2960A 3Gb/s, HD, SD SDI Receiver

Data Sheet

54384 - 2

September 2012

www.semtech.com

Contents

Key Features ........................................................................................................................................................1

Applications.........................................................................................................................................................1

Description...........................................................................................................................................................1

Functional Block Diagram ..............................................................................................................................2

1. Pin Out...............................................................................................................................................................7

1.1 Pin Assignment ..................................................................................................................................7

1.2 Pin Descriptions ................................................................................................................................7

2. Electrical Characteristics ......................................................................................................................... 14

2.1 Absolute Maximum Ratings ....................................................................................................... 14

2.2 Recommended Operating Conditions .................................................................................... 14

2.3 DC Electrical Characteristics ..................................................................................................... 15

2.4 AC Electrical Characteristics ..................................................................................................... 17

3. Input/Output Circuits ............................................................................................................................... 22

4. Detailed Description.................................................................................................................................. 25

4.1 Functional Overview .................................................................................................................... 25

4.2 SMPTE 425M Mapping - 3G Level A and Level B Formats ............................................... 25

4.2.1 Level A Mapping................................................................................................................ 25

4.2.2 Level B Mapping ................................................................................................................ 26

4.3 Serial Digital Input ........................................................................................................................ 26

4.4 Serial Digital Loop-Through Output ........................................................................................ 26

4.5 Serial Digital Reclocker ............................................................................................................... 27

4.5.1 PLL Loop Bandwidth ........................................................................................................ 27

4.6 External Crystal/Reference Clock ........................................................................................... 28

4.7 Lock Detect ...................................................................................................................................... 29

4.7.1 Asynchronous Lock .......................................................................................................... 30

4.7.2 Signal Interruption............................................................................................................ 31

4.8 SMPTE Functionality .................................................................................................................... 31

4.8.1 Descrambling and Word Alignment ........................................................................... 31

4.9 Parallel Data Outputs ................................................................................................................... 32

4.9.1 Parallel Data Bus Buffers................................................................................................. 32

4.9.2 Parallel Output in SMPTE Mode ................................................................................... 35

4.9.3 Output Data Format in DVB-ASI Mode...................................................................... 35

4.9.4 Parallel Output in Data-Through Mode ..................................................................... 36

4.9.5 Parallel Output Clock (PCLK)......................................................................................... 36

4.9.6 DDR Parallel Clock Timing ............................................................................................. 37

4.10 Timing Signal Generator ........................................................................................................... 39

4.10.1 Manual Switch Line Lock Handling.......................................................................... 40

4.10.2 Automatic Switch Line Lock Handling .................................................................... 41

4.10.3 Switch Line Lock Handling During Level B to Level A Conversion ............... 41

4.11 Programmable Multi-function Outputs ............................................................................... 43

4.12 H:V:F Timing Signal Generation ............................................................................................ 44

4.12.1 CEA-861 Timing Generation ....................................................................................... 46

4.13 Automatic Video Standards Detection ................................................................................ 52

4.13.1 2K Support......................................................................................................................... 56

GS2960A 3Gb/s, HD, SD SDI Receiver

Data Sheet

54384 - 2

September 2012

3 of 99

4.14 Data Format Detection & Indication ..................................................................................... 56

4.15 EDH Detection .............................................................................................................................. 57

4.15.1 EDH Packet Detection ................................................................................................... 57

4.15.2 EDH Flag Detection ........................................................................................................ 58

4.16 Video Signal Error Detection & Indication ......................................................................... 58

4.16.1 TRS Error Detection........................................................................................................ 60

4.16.2 Line Based CRC Error Detection ................................................................................ 60

4.16.3 EDH CRC Error Detection............................................................................................. 61

4.16.4 HD & 3G Line Number Error Detection ................................................................... 61

4.17 Ancillary Data Detection & Indication ................................................................................. 61

4.17.1 Programmable Ancillary Data Detection................................................................ 63

4.17.2 SMPTE 352M Payload Identifier ................................................................................ 64

4.17.3 Ancillary Data Checksum Error ................................................................................. 65

4.17.4 Video Standard Error..................................................................................................... 66

4.18 Signal Processing ......................................................................................................................... 66

4.18.1 TRS Correction & Insertion........................................................................................... 67

4.18.2 Line Based CRC Correction & Insertion ................................................................... 68

4.18.3 Line Number Error Correction & Insertion ............................................................. 68

4.18.4 ANC Data Checksum Error Correction & Insertion ............................................. 68

4.18.5 EDH CRC Correction & Insertion ............................................................................... 68

4.18.6 Illegal Word Re-mapping ............................................................................................. 69

4.18.7 TRS and Ancillary Data Preamble Remapping...................................................... 69

4.18.8 Ancillary Data Extraction............................................................................................. 69

4.18.9 Level B to Level A Conversion .................................................................................... 73

4.19 GSPI - HOST Interface ................................................................................................................ 74

4.19.1 Command Word Description ...................................................................................... 75

4.19.2 Data Read or Write Access........................................................................................... 75

4.19.3 GSPI Timing....................................................................................................................... 76

4.20 Host Interface Register Maps .................................................................................................. 78

4.21 JTAG Test Operation .................................................................................................................. 92

4.22 Device Power-up ......................................................................................................................... 93

4.23 Device Reset .................................................................................................................................. 93

4.24 Standby Mode .............................................................................................................................. 93

5. Application Reference Design ............................................................................................................... 94

5.1 Typical Application Circuit ........................................................................................................ 94

6. References & Relevant Standards ......................................................................................................... 95

7. Package & Ordering Information .......................................................................................................... 96

7.1 Package Dimensions ..................................................................................................................... 96

7.2 Packaging Data ............................................................................................................................... 97

7.3 Marking Diagram ........................................................................................................................... 97

7.4 Solder Reflow Profiles .................................................................................................................. 98

7.5 Ordering Information ................................................................................................................... 98

Revision History .............................................................................................................................................. 98

GS2960A 3Gb/s, HD, SD SDI Receiver

Data Sheet

54384 - 2

September 2012

4 of 99

List of Figures

Figure 3-1: Digital Input Pin with Schmitt Trigger............................................................................... 22

Figure 3-2: Bidirectional Digital Input/Output Pin.............................................................................. 22

Figure 3-3: Bidirectional Digital Input/Output Pin with programmable drive strength......... 23

Figure 3-4: XTAL1/XTAL2/XTAL-OUT ................................................................................................... 23

Figure 3-5: VBG .............................................................................................................................................. 23

Figure 3-6: LB_CONT .................................................................................................................................... 24

Figure 3-7: Loop Filter .................................................................................................................................. 24

Figure 3-8: SDI/SDI and TERM .................................................................................................................. 24

Figure 3-9: SDO/SDO .................................................................................................................................... 24

Figure 4-1: Level A Mapping ...................................................................................................................... 25

Figure 4-2: Level B Mapping ...................................................................................................................... 26

Figure 4-3: 27MHz Clock Sources ............................................................................................................ 29

Figure 4-4: PCLK to Data and Control Signal Output Timing - SDR Mode 1 .............................. 32

Figure 4-5: PCLK to Data and Control Signal Output Timing - SDR Mode 2 .............................. 33

Figure 4-6: PCLK to Data and Control Signal Output Timing - DDR Mode ................................. 34

Figure 4-7: DDR Video Interface - 3G Level A ..................................................................................... 37

Figure 4-8: DDR Video Interface - 3G Level B ...................................................................................... 38

Figure 4-9: Delay Adjustment Ranges .................................................................................................... 39

Figure 4-10: Switch Line Locking on a Non-Standard Switch Line ............................................... 40

Figure 4-11: H:V:F Output Timing - 3G Level A and HDTV 20-bit Mode .................................... 44

Figure 4-12: H:V:F Output Timing - 3G Level A and HDTV 10-bit Mode

3G Level B 20-bit Mode, each 10-bit stream ......................................................................................... 44

Figure 4-13: H:V:F Output Timing - 3G Level B 10-bit Mode .......................................................... 45

Figure 4-14: H:V:F Output Timing - HD 20-bit Output Mode ......................................................... 45

Figure 4-15: H:V:F Output Timing - HD 10-bit Output Mode ......................................................... 45

Figure 4-16: H:V:F Output Timing - SD 20-bit Output Mode .......................................................... 45

Figure 4-17: H:V:F Output Timing - SD 10-bit Output Mode .......................................................... 45

Figure 4-18: H:V:DE Output Timing 1280 x 720p @ 59.94/60 (Format 4) ................................... 47

Figure 4-19: H:V:DE Output Timing 1920 x 1080i @ 59.94/60 (Format 5) ................................. 47

Figure 4-20: H:V:DE Output Timing 720 (1440) x 480i @ 59.94/60 (Format 6&7) .................... 48

Figure 4-21: H:V:DE Output Timing 1280 x 720p @ 50 (Format 19) ............................................. 48

Figure 4-22: H:V:DE Output Timing 1920 x 1080i @ 50 (Format 20) ........................................... 49

Figure 4-23: H:V:DE Output Timing 720 (1440) x 576 @ 50 (Format 21 & 22) ........................... 50

Figure 4-24: H:V:DE Output Timing 1920 x 1080p @ 59.94/60 (Format 16) .............................. 50

Figure 4-25: H:V:DE Output Timing 1920 x 1080p @ 50 (Format 31) .......................................... 51

Figure 4-26: H:V:DE Output Timing 1920 x 1080p @ 23.94/24 (Format 32) .............................. 51

Figure 4-27: H:V:DE Output Timing 1920 x 1080p @ 25 (Format 33) .......................................... 52

Figure 4-28: H:V:DE Output Timing 1920 x 1080p @ 29.97/30 (Format 34) .............................. 52

Figure 4-29: 2K Feature Enhancement ................................................................................................... 56

Figure 4-30: Y/1ANC and C/2ANC Signal Timing .............................................................................. 63

Figure 4-31: Ancillary Data Extraction - Step A .................................................................................. 70

Figure 4-32: Ancillary Data Extraction - Step B ................................................................................... 71

Figure 4-33: Ancillary Data Extraction - Step C .................................................................................. 71

Figure 4-34: Ancillary Data Extraction - Step D .................................................................................. 72

Figure 4-35: GSPI Application Interface Connection ........................................................................ 74

Figure 4-36: Command Word Format ..................................................................................................... 75

Figure 4-37: Data Word Format ................................................................................................................ 76

Figure 4-38: Write Mode .............................................................................................................................. 76

Figure 4-39: Read Mode ............................................................................................................................... 76

Figure 4-40: GSPI Time Delay .................................................................................................................... 76

Figure 4-41: In-Circuit JTAG ...................................................................................................................... 92

Figure 4-42: System JTAG ........................................................................................................................... 92

Figure 4-43: Reset Pulse ............................................................................................................................... 93

Figure 7-1: Pb-free Solder Reflow Profile .............................................................................................. 98

GS2960A 3Gb/s, HD, SD SDI Receiver

Data Sheet

54384 - 2

September 2012

5 of 99

Recommended Resources

Dual-frequency oscillation circuit diagram composed of audio decoder

Two-phase stepper motor drive system circuit

electronic fireworks

FT2275 (universal) infrared remote control decoding circuit

l 500v isolation circuit for D/A slave converter

Three-phase motor intermittent starting circuit

Maple r5 board is not recognized and is displayed as Unknown Device: I and another classmate are in this situation. We are using Win7, and the device manager shows "Unknown Device". Both drivers cannot be installed. They cannot be recognized in Ubuntu. I asked several ...; nilennoct stm32/stm8

Please recommend a GPS module to me: My graduation project is to make a smart car based on ultrasonic obstacle avoidance and GPS navigation, but I don't know which GPS module to use on the car. Can anyone recommend one? The price is arou...; loosie MCU

I'm so depressed. What's the problem?: Use this to set the clock SysCtlClockSet(SYSCTL_SYSDIV_1 | SYSCTL_USE_OSC | SYSCTL_OSC_MAIN | SYSCTL_XTAL_6MHZ); Then use the serial port, set the baud rate to 115200, it can be displayed normally, an...; panyaoem Microcontroller MCU

[RISC-V MCU CH32V103 Review] - 4: EXTI starts the troubleshooting journey: [i=s]This post was last edited by MianQi on 2021-2-10 10:39[/i]I tested the content of this document: "CH32V103 Application Tutorial - EXTI", and found two errors:../EXTI/main.c:3:30: error: 'NVIC_Pri...; MianQi Domestic Chip Exchange

Daily management of a small business owner: 1. How do small companies retain backbone personnel:2. About authorization3. Some money cannot be saved5. About recruitment6. The boss should try to play the good cop7. Relatives in the company8. Bein...; 安_然 Analog electronics

webcast:how to down?: http://www.microsoft.com/china/msdn/events/webcasts/shared/webcast/downloadarchive.aspx This place cannot be downloaded. I want to download the WINCE video but cannot? ??...; readeagle Embedded System

Shortcut: 00 01 02 03 04 05 06 07 08 09 0A 0C 0F 0J 0L 0M 0R 0S 0T 0Z 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 1H 1K 1M 1N 1P 1S 1T 1V 1X 1Z 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 2G 2K 2M 2N 2P 2Q 2R 2S 2T 2W 2Z 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F 3G 3H 3J 3K 3L 3M 3N 3P 3R 3S 3T 3V 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4M 4N 4P 4S 4T 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5E 5G 5H 5K 5M 5N 5P 5S 5T 5V 60 61 62 63 64 65 66 67 68 69 6A 6C 6E 6F 6M 6N 6P 6R 6S 6T 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7M 7N 7P 7Q 7V 7W 7X 80 81 82 83 84 85 86 87 88 89 8A 8D 8E 8L 8N 8P 8S 8T 8W 8Y 8Z 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9F 9G 9H 9L 9S 9T 9W

Popular Components