NanoAmp Solutions, Inc.
1982 Zanker Road, San Jose, CA 95112
ph: 408-573-8878, FAX: 408-573-8877
www.nanoamp.com
EM033C08
EM033C08
Low Power 32Kx8 SRAM in a 32 pin ROM Pinout Compatible Package
Overview
The EM033C08 is an integrated memory device
containing a low power 256 Kbit Static Random
Access Memory organized as 32,768 words by 8
bits. The device is fabricated using an advanced
CMOS process and NanoAmp’s high-speed/low-
power circuit technology. This device is designed
to be quite effective in battery powered products
with it’s very low operating and standby currents. It
is also capable of full operation at voltages as low
as 1.5 volts. The device pinout is fully compatible
with NanoAmp’s EM02R2XX family of Combination
RAM and ROM products making it very easy to
substitute an SRAM only device where the ROM is
unneccessary in the application. This device is
extremely stable over broad temperature and volt-
age ranges.
Features
•
•
•
•
•
•
•
Extended Operating Voltage Range
1.5 to 3.6 V
Very Low Standby Voltage
1.2 V
Extended Temperature Range
-20
o
to +80
o
C
Fast Cycle Time
100 ns (@ 2.7V)
Very Low Operating Current
I
CC
< 1 mA typical at 3V, 1 Mhz
Very Low Standby Current
I
SB
= 100 nA typical
Available in 32-pin STSOP or TSOP
package
FIGURE 1: Pin Configuration
A11
A9
A8
A13
A14
NC
CE
VCC
WE
NC
NC
A12
A7
A6
A5
A4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OE
A10
NC
D7
D6
D5
D4
D3
VSS
D2
D1
D0
A0
A1
A2
A3
TABLE 1: Pin Descriptions
Pin Name
A0-A14
D0-D7
CE
OE
WE
V
CC
V
SS
NC
Pin Function
Address Inputs
Data Inputs/Outputs
Chip Enable (Active Low)
Output Enable (Active Low)
Write Enable (Active Low)
Power
Ground
Not Connected (Floating)
EM033C08
STSOP, TSOP
FIGURE 2: Operating Envelope
8 Mhz
8
Typical I
CC
(mA)
6
5 Mhz
4
2
0
0
1
2
V
CC
(V)
3
4
2.5 Mhz
1 Mhz
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NanoAmp Solutions
FIGURE 3: Functional Block Diagram
Input/
Address
Inputs
A
0
- A
14
Address
Decode
Logic
32K x 8
RAM Array
Output
Mux
and
Buffers
D0 - D7
Data I/O
EM033C08
CE
WE
OE
Control
Logic
FIGURE 4: Functional Description
CE
H
L
L
L
WE
X
H
H
L
OE
X
H
L
X
D0-D7
High Z
High Z
Data Out
Data In
MODE
Standby
Standby
READ
WRITE
POWER
Standby
Standby*
Active -> Standby*
Active -> Standby*
*The device will consume active power in this mode whenever addresses are changed
TABLE 2: Absolute Maximum Ratings*
Item
Voltage on any pin relative to V
SS
Voltage on V
CC
Supply Relative to V
SS
Power Dissipation
Storage Temperature
Operating Temperature - Extended Commercial
Symbol
V
IN,OUT
V
CC
P
D
T
STG
T
A
Rating
–0.3 to V
CC
+0.3
–0.3 to 4.6
500
–40 to +125
-20 to +80
Unit
V
V
mW
o
C
o
C
*Stresses greater than those listed above may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those indicated in the operating section of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
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EM033C08
TABLE 3: Operating Characteristics (Over specified temperature range)
Item
Supply Voltage
Data Retention Voltage
Input High Voltage
Input Low Voltage
Output High Voltage
Output Low Voltage
Input Leakage Current
Output Leakage Current
Operating Supply
Current (Note 1)
Standby Current (Note 2)
Notes:
Note 1. Operating current is a linear function of frequency and voltage. You may calculate operating current using the
formula shown with operating frequency (f) expressed in Mhz and operating voltage (V) in volts. Example: Operating
at 2 Mhz and 2.0 volts will draw a maximum current of 0.3*2*2 = 1.2 mA.
Note 2. This device assumes a standby mode whenever Chip Enable (CE) is disabled (high). It will also automatically
go into a standby mode whenever all input signals are quiescent (not toggling) whenever an access or write cycle is
completed regardless of the state CE. In order to achieve low standby current all input levels must be within 0.2 volts
of either V
CC
or GND.
Symbol
V
CC
V
DR
V
IH
V
IL
V
OH
V
OL
I
LI
I
LO
I
CC
I
SB
I
OH
= 200
µA
I
OL
= –200
µA
V
IN
= 0 to V
CC
OE = V
IH
or CE = 1
V
IN
= V
CC
or 0V, CE = 0
V
IN
= V
CC
or 0V
CE = V
CC
Test Conditions
Min.
1.5
1.2
0.7V
CC
–0.3
V
CC
–0.2
0.2
1
1
0.3 * f * V
10
Max.
3.6
3.6
V
CC
+0.3
0.3V
CC
Unit
V
V
V
V
V
V
µA
µA
mA
µA
TABLE 4: Capacitance*
Item
Input Capacitance
I/O Capacitance
Symbol
C
IN
C
I/O
Test Condition
V
IN
= 0V, f = 1 Mhz, T
A
= 25
o
C
V
IN
= 0V, f = 1 Mhz, T
A
= 25
o
C
Min
Max
5
5
Unit
pF
pF
Note: These parameters are verified in device characterization and are not 100% tested
TABLE 5: Timing Test Conditions
Item
Input Pulse Level
Input Rise and Fall Time
Input and Output Timing Reference Levels
Output Load
Operating Temperature (Unless otherwise stated)
0.1V
CC
to 0.9 V
CC
5ns
0.5V
CC
CL = 30pF
-20 to +80
o
C
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EM033C08
TABLE 6: Timing
Item
Read Cycle Time
Address-Chip Enable Setup Time
Address-Chip Enable Hold Time
Address Access Time
Chip Enable Access Time
Output Enable to Valid Output
Chip Enable to Low-Z output
Output Enable to Low-Z Output
Chip Enable to High-Z Output
Output Disable to High-Z Output
Output Hold from Address Change
Write Cycle Time
Chip Enable to End of Write
Address Valid to End of Write
Address Set-Up Time
Write Pulse Width
Write Recovery Time
Write to High-Z Output
Data to Write Time Overlap
Data Hold from Write Time
End Write to Low-Z Output
Symbol
t
RC
t
ASC
t
AHC
t
AA
t
CE
t
OE
t
LZ
t
OLZ
t
HZ
t
OHZ
t
OH
t
WC
t
CW
t
AW
t
AS
t
WP
t
WR
t
WHZ
t
DW
t
DH
t
OW
Min/Max
Min
Min
Min
Max
Max
Max
Min
Min
Min
Max
Min
Max
Min
Min
Min
Min
Min
Min
Min
Min
Max
Min
Min
Min
1.5V
750
-80
600
750
750
250
0
0
0
100
0
100
40
750
750
750
0
400
0
0
150
400
75
40
1.8V
250
-40
200
250
250
70
0
0
0
50
0
50
20
250
250
250
0
150
0
0
70
150
35
20
2.4V
150
-30
120
150
150
50
0
0
0
40
0
40
15
150
150
150
0
75
0
0
50
75
20
15
2.7-3.6V
100
-20
75
100
100
30
0
0
0
25
0
25
10
100
100
100
0
50
0
0
30
50
15
10
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
FIGURE 5: Read Cycle Timing (WE = V
IH
)
t
RC
A0-A14
t
AA
t
ASC
CE
t
CS
OE
t
LZ
D0-D7
t
OE
t
OLZ
Data Valid
t
OHZ
t
HZ
t
AHC
t
OH
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EM033C08
FIGURE 6: Write Cycle Timing (OE fixed)
t
WC
A0-A14
t
AW
t
CW
CE
t
AS
WE
t
DW
Data In
t
WHZ
Data Out
High-Z
Data Valid
t
OW
t
ASC
t
AHC
t
WP
t
DH
t
OH
t
WR
FIGURE 7: Write Cycle Timing (OE clock)
t
WC
A0-A14
t
ASC
OE
t
AW
t
CW
CE
t
WP
WE
t
AS
t
WHZ
t
DW
Data
Data In
t
OHZ
High-Z
Data Out
t
OW
t
DH
t
AHC
t
WR
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