DISCRETE SEMICONDUCTORS
DATA SHEET
BF998; BF998R
Silicon N-channel dual-gate
MOS-FETs
Product specification
Supersedes data of April 1991
File under Discrete Semiconductors, SC07
1996 Aug 01
Philips Semiconductors
Product specification
Silicon N-channel dual-gate MOS-FETs
FEATURES
•
Short channel transistor with high forward transfer
admittance to input capacitance ratio
•
Low noise gain controlled amplifier up to 1 GHz.
APPLICATIONS
•
VHF and UHF applications with 12 V supply voltage,
such as television tuners and professional
communications equipment.
Top view
handbook, halfpage
BF998; BF998R
4
3
g
2
g
1
d
1
2
s,b
MAM039
DESCRIPTION
Depletion type field effect transistor in a plastic
microminiature SOT143 or SOT143R package with source
and substrate interconnected. The transistors are
protected against excessive input voltage surges by
integrated back-to-back diodes between gates and
source.
CAUTION
The device is supplied in an antistatic package. The
gate-source input must be protected against static
discharge during transport or handling.
Marking code:
MOp.
Fig.1
Simplified outline (SOT143)
and symbol; BF998.
handbook, halfpage
d
4
g2
g1
3
PINNING
PIN
1
2
3
4
SYMBOL
s, b
d
g
2
g
1
source
drain
gate 2
gate 1
DESCRIPTION
Top view
2
1
s,b
MAM040
Marking code:
MOp.
Fig.2
Simplified outline (SOT143R)
and symbol; BF998R.
QUICK REFERENCE DATA
SYMBOL
V
DS
I
D
P
tot
y
fs
C
ig1-s
C
rs
F
T
j
drain current
total power dissipation
forward transfer admittance
input capacitance at gate 1
reverse transfer capacitance
noise figure
operating junction temperature
f = 1 MHz
f = 800 MHz
PARAMETER
drain-source voltage
CONDITIONS
−
−
−
24
2.1
25
1
−
TYP.
MAX.
12
30
200
−
−
−
−
150
V
mA
mW
mS
pF
fF
dB
°C
UNIT
1996 Aug 01
2
Philips Semiconductors
Product specification
Silicon N-channel dual-gate MOS-FETs
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
SYMBOL
V
DS
I
D
±I
G1
±I
G2
P
tot
P
tot
T
stg
T
j
Notes
1. Device mounted on a ceramic substrate, 8 mm
×
10 mm
×
0.7 mm.
2. Device mounted on a printed-circuit board.
PARAMETER
drain-source voltage
drain current
gate 1 current
gate 2 current
total power dissipation; BF998
up to T
amb
= 60
°C;
see Fig.3; note 1
up to T
amb
= 50
°C;
see Fig.3; note 2
total power dissipation; BF998R up to T
amb
= 50
°C;
see Fig.4; note 1
storage temperature
operating junction temperature
CONDITIONS
−
−
−
−
−
−
−
−65
−
BF998; BF998R
MIN.
MAX.
12
30
10
10
200
200
200
+150
150
V
UNIT
mA
mA
mA
mW
mW
mW
°C
°C
MLA198
MGA002
handbook, halfpage
handbook, halfpage
200
Ptot max
(mW)
(2)
(1)
200
Ptot max
(mW)
100
100
0
0
100
Tamb (
o
C)
200
0
0
100
Tamb (°C)
200
(1) Ceramic substrate.
(2) Printed-circuit board.
Fig.3 Power derating curves; BF998.
Fig.4 Power derating curve; BF998R.
1996 Aug 01
3
Philips Semiconductors
Product specification
Silicon N-channel dual-gate MOS-FETs
THERMAL CHARACTERISTICS
SYMBOL
R
th j-a
R
th j-a
Notes
1. Device mounted on a ceramic substrate, 8 mm
×
10 mm
×
0.7 mm.
2. Device mounted on a printed-circuit board.
STATIC CHARACTERISTICS
T
j
= 25
°C;
unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
V
G2-S
= V
DS
= 0; I
G1-SS
=
±10
mA
V
G1-S
= V
DS
= 0; I
G2-SS
=
±10
mA
V
G2-S
= 4 V; V
DS
= 8 V; I
D
= 20
µA
V
G1-S
= 0; V
DS
= 8 V; I
D
= 20
µA
PARAMETER
thermal resistance from junction to ambient in free air; BF998
BF998; BF998R
CONDITIONS
note 1
note 2
VALUE
460
500
500
UNIT
K/W
K/W
K/W
thermal resistance from junction to ambient in free air; BF998R note 1
MIN.
6
6
−
−
2
−
−
MAX.
20
20
2.0
1.5
18
50
50
UNIT
V
V
V
V
mA
nA
nA
±V
(BR)G1-SS
gate 1-source breakdown voltage
±V
(BR)G2-SS
gate 2-source breakdown voltage
−V
(P)G1-S
−V
(P)G2-S
I
DSS
±I
G1-SS
±I
G2-SS
Note
1. Measured under pulse condition.
gate 1-source cut-off voltage
gate 2-source cut-off voltage
drain-source current
gate 1 cut-off current
gate 2 cut-off current
V
G2-S
= 4 V; V
DS
= 8 V; V
G1-S
= 0; note 1
V
G2-S
= V
DS
= 0; V
G1-S
=
±5
V
V
G1-S
= V
DS
= 0; V
G2-S
=
±5
V
DYNAMIC CHARACTERISTICS
Common source; T
amb
= 25
°C;
V
DS
= 8 V; V
G2-S
= 4 V; I
D
= 10 mA.
SYMBOL
y
fs
C
ig1-s
C
ig2-s
C
os
C
rs
F
PARAMETER
forward transfer admittance
input capacitance at gate 1
input capacitance at gate 2
output capacitance
reverse transfer capacitance
noise figure
f = 1 kHz
f = 1 MHz
f = 1 MHz
f = 1 MHz
f = 1 MHz
f = 200 MHz; G
S
= 2 mS; B
S
= B
Sopt
f = 800 MHz; G
S
= 3.3 mS; B
S
= B
Sopt
CONDITIONS
MIN.
21
−
−
−
−
−
−
TYP.
24
2.1
1.2
1.05
25
0.6
1.0
MAX.
−
2.5
−
−
−
−
−
UNIT
mS
pF
pF
pF
fF
dB
dB
1996 Aug 01
4
Philips Semiconductors
Product specification
Silicon N-channel dual-gate MOS-FETs
BF998; BF998R
handbook, halfpage
I
24
MGE813
D
(mA)
handbook, halfpage
I
24
MGE815
VG1-S =
0.4 V
0.3 V
20
D
(mA)
20
3V
VG2-S = 4 V
2V
1V
16
0.2 V
0.1 V
0V
16
12
12
8
−0.1
V
−0.2
V
8
0V
4
0
0
2
4
6
8
VDS (V)
−0.3
V
−0.4
V
−0.5
V
10
4
0
−1
0
VG1 (V)
1
V
G2-S
= 4 V; T
amb
= 25
°C.
V
DS
= 8 V; T
amb
= 25
°C.
Fig.5 Output characteristics; typical values.
Fig.6 Transfer characteristics; typical values.
handbook, halfpage
I
24
MGE814
MGE811
D
(mA)
20
handbook, halfpage
30
max
typ
|yfs|
(mS)
24
4V
3V
2V
1V
16
18
12
min
12
8
6
VG2-S = 0 V
0
0
4
8
12
16
ID (mA)
20
0.5 V
4
0
−1600
−1200
−800
−400
0
VG1 (mV)
400
V
DS
= 8 V; V
G2-S
= 4 V; T
amb
= 25
°C.
V
DS
= 8 V; T
amb
= 25
°C.
Fig.7
Drain current as a function of gate 1
voltage; typical values.
Fig.8
Forward transfer admittance as a function of
drain current; typical values.
1996 Aug 01
5
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