EEWORLDEEWORLDEEWORLD

Part Number

Search

K4C89183AF-GCG7

Description
DDR DRAM, 16MX18, 0.5ns, CMOS, PBGA60
Categorystorage    storage   
File Size2MB,67 Pages
ManufacturerSAMSUNG
Websitehttp://www.samsung.com/Products/Semiconductor/
Download Datasheet Parametric View All

K4C89183AF-GCG7 Overview

DDR DRAM, 16MX18, 0.5ns, CMOS, PBGA60

K4C89183AF-GCG7 Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
MakerSAMSUNG
package instructionBGA, BGA60,6X15,40
Reach Compliance Codecompliant
Maximum access time0.5 ns
Maximum clock frequency (fCLK)400 MHz
I/O typeCOMMON
interleaved burst length2,4
JESD-30 codeR-PBGA-B60
JESD-609 codee0
memory density301989888 bit
Memory IC TypeDDR DRAM
memory width18
Number of terminals60
word count16777216 words
character code16000000
Maximum operating temperature70 °C
Minimum operating temperature
organize16MX18
Output characteristics3-STATE
Package body materialPLASTIC/EPOXY
encapsulated codeBGA
Encapsulate equivalent codeBGA60,6X15,40
Package shapeRECTANGULAR
Package formGRID ARRAY
power supply1.8,2.5 V
Certification statusNot Qualified
Continuous burst length2,4
surface mountYES
technologyCMOS
Temperature levelCOMMERCIAL
Terminal surfaceTin/Lead (Sn/Pb)
Terminal formBALL
Terminal pitch1 mm
Terminal locationBOTTOM

K4C89183AF-GCG7 Preview

K4C89183AF
288Mb Network-DRAM-II Specification
Version 0.11
- 1 -
REV. 0.11 Apr. 2003
K4C89183AF
Revision History
Version 0.0 (Oct. 2002)
- First Release
Version 0.01 (Nov. 2002)
- Changed die revision from D-die to F-die
- Corrected typo
- Corrected DQS to DS and QS(DQS -> DS and QS) in AC timing table and timing diagram.
Version 0.1 (Apr. 2003)
- Added 800Mbps(400Mhz) product
- Changed operating temperature from Ta to Tc.
- Changed capacitance of ADDR/CMD/CLK
From
Min
Addr/CMD/CLK
1.5
Max
2.5
Min
1.5
To
Max
3.0
- Changed tDSS(DS input Falling Edge to Clock Setup Time)
From
F6
CL4
CL5
CL6
CL7
0.9
0.9
0.9
-
FB
0.9
0.9
0.9
-
F5
1.0
1.0
1.0
-
G7
0.75
0.75
0.75
0.75
F6
0.75
0.75
0.75
-
To
FB
0.8
0.8
0.8
-
F5
1.0
1.0
1.0
-
- Added CL7 for 800Mbps
- Deleted TSOP package outline
Version 0.11 (Apr. 2003)
- Corrected typo in page 3.(Deleted bi-directional strobe)
-
Corrected min. Vref to VDDQ/2x95% in page 7
- 2 -
REV. 0.11 Apr. 2003
K4C89183AF
4,194,304-WORDS x 4 BANKS x 18-BITS DOUBLE DATA RATE Network-DRAM
DESCRIPTION
K4C89183AF is a CMOS Double Data Rate Network-DRAM containing 301,989,888 memory cells. K4C89183AF is organized as
4,194,304-words x 4 banks x18 bits. K4C89183AF feature a fully synchronous operation referenced to clock edge whereby all opera-
tions are synchronized at a clock input which enables high performance and simple user interface coexistence. K4C89183AF can oper-
ate fast core cycle compared with regular DDR SDRAM.
K4C89183AF is suitable for Server, Network and other applications where large memory density and low power consumption are
required. The Output Driver for Network-DRAM is capable of high quality fast data transfer under light loading condition.
FEATURES
Parameter
CL = 4
t
CK
Clock Cycle Time (min)
CL = 5
CL = 6
CL = 7
t
RC
Random Read/Write Cycle Time (min)
t
RAC
Random Access Time (min)
I
DD1S
Operating Current (single bank) (max)
I
DD2S
Power Down Current (max)
I
DD3S
Self-Refresh Current (max)
K4C89183AF
G7
4.0 ns
3.33 ns
3.0ns
2.5ns
20.0 ns
20.0 ns
TBD
TBD
TBD
F6
4.0 ns
3.33 ns
3.0ns
-
20.0 ns
20.0 ns
TBD
TBD
TBD
FB
4.5 ns
3.75 ns
3.33 ns
-
22.5 ns
22.5 ns
TBD
TBD
TBD
F5
5.0 ns
4.5 ns
4.0 ns
-
25 ns
25 ns
TBD
TBD
TBD
Fully Synchronous Operation
- Double Data Rate (DDR)
- Data input/output are synchronized with both edges of DS / QS.
- Differential Clock (CLK and CLK) inputs
- CS, FN and all address input signals are sampled on the positive edge of CLK.
- Output data (DQs and QS) is aligned to the crossings of CLK and CLK.
Fast clock cycle time of 2.5 ns minimum
- Clock : 400 MHz maximum
- Data : 800 Mbps/pin maximum
Quad Independent Banks operation
Fast cycle and Short Latency
Uni-directional Data Strobe
Distributed Auto-Refresh cycle in 3.9us
Self-Refresh
Power Down Mode
Variable Write Length Control
Write Latency = CAS Latency-1
Programable CAS Latency and Burst Length
- CAS Laatency = 4, 5, 6,7
- Burst Length = 2, 4
Organization : 4,194,304 words x 4 banks x 18 bits
Power Supply Voltage V
DD
: 2.5V
±
0.125V
V
DDQ
: 1.4V
1.9V
1.8V CMOS I/O comply with SSTL - 1.8 (half strength driver) and HSTL
Package : 60Ball BGA, 1.0mm x 1.0mm Ball pitch
Notice : Network-DRAM is trademark of Samsung Electronics., Co LTD
- 3 -
REV. 0.11 Apr. 2003
K4C89183AF
Pin Names
Pin
A0 ~ A14
BA0, BA1
DQ0 ~ DQ17
CS
FN
PD
CLK, CLK
DS/QS
VDD
V
SS
V
DDQ
V
SSQ
V
REF
NC
Name
Address Input
Bank Address
Data Input/Output
Chip Select
Function Control
Power Down Control
Clock Input
C
Write/Read data strobe
Power (+2.5V)
Ground
E
Power (+1.8V)
(for I/O buffer)
Ground
(for I/O buffer)
Reference Voltage
No Connection
H
J
K
L
M
N
P
R
DQ9
V
REF
CLK
A12
A11
A8
A5
V
SS
DS
V
ss
CLK
PD
A9
A7
A6
A4
QS
V
DD
FN
CS
BA1
A0
A2
A3
DQ8
A14
A13
NC
BA0
A10
A1
V
DD
F
G
DQ12
DQ11
DQ10
V
ss
Q
V
DD
Q
V
ss
Q
V
DD
Q
V
ss
Q
V
DD
Q
DQ5
DQ6
DQ7
D
DQ14
DQ15
V
DD
Q
DQ13
V
ss
Q
DQ4
DQ2
DQ3
B
DQ16
V
ss
Q
V
DD
Q
DQ1
A
1
Index
V
ss
DQ17
DQ0
V
DD
2
3
4
5
6
PIN ASSIGNMENT
(TOP VIEW)
ball pitch=1.0 x 1.0mm
x18
- 4 -
REV. 0.11 Apr. 2003
K4C89183AF
Block Diagram
CLK
CLK
PD
DLL
CLOCK
BUFFER
To Each Block
BANK #3
CS
FN
COMMAND
DECODER
CONTROL
SIGNAL
GENERATOR
BANK #2
DATA
CONTROL AND LATCH
CIRCUIT
READ
DATA
BUFFER
WRITE
DATA
BUFFER
DQ BUFFER
DQ0 ~ DQ17
BANK #1
BANK #0
ROW DECODER
A0 ~ A14
BA0, BA1
ADDRESS
BUFFER
MODE
REGISTER
MEMORY
CELL
ARRAY
UPPER ADDRESS
LATCH
LOWER ADDRESS
LATCH
COLUMN DECODER
REFRESH
COUNTER
BURST
COUNTER
WRITE ADDRESS
LATCH
ADDRESS
COMPARATOR
DS
QS
Note :
The K4C89183AD configuration is 4 Bank of 32768 x 128 x 18 of cell array with the DQ pins numbered DQ0~DQ17.
- 5 -
REV. 0.11 Apr. 2003
TTL to 232, 232 to USB, I am confused
My connection method is: board + TTL to RS232 + RS232 to USB + PC. "+" represents connection. Is there any problem with this conversion? Why can't I receive data? I can receive data by directly connec...
cgl123456 Embedded System
Single chip microcomputer c51 frequency meter
Is there any code for the C51 frequency counter? It would be best if it uses interrupt 2. Thank you....
huangbuben Embedded System
Is there a chip for sle4442 contactless IC card?
As the title says, I only want the chip, not the card. I have been looking for it for a long time, but I can't find it. So I want to use software simulation, but the result is not very ideal. I would ...
堕落小生 Microchip MCU
Help me choose the AD conversion module
Now I need an AD conversion chip, the requirement is that it must have at least 3 inputs, and the data output should be 12 bits at best, but 8 bits is also OK. I would like to ask for your advice... T...
wqfwh MCU
About 555
Can someone tell me if the 555 output can drive the 555?...
lop Analog electronics
MSP430 assembly code, please translate it into C language code
Thank you all, this is the glass breaking code based on MSP430. I want to transplant the algorithm. Please help me translate. Thank you. 'My qq292883168'; --COPYRIGHT--,BSD; Copyright (c) 2012, Texas ...
曾祥裕 Microcontroller MCU

EEWorld
subscription
account

EEWorld
service
account

Automotive
development
circle

Robot
development
community

Index Files: 2250  177  2281  1953  1064  46  4  40  22  15 
Datasheet   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Room 1530, 15th Floor, Building B, No. 18 Zhongguancun Street, Haidian District, Beijing Telephone: (010) 82350740 Postal Code: 100190
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved 京ICP证060456号 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号