FemtoClock NG Crystal-to-3.3V, 2.5V
Multiple Frequency Clock Generator
w/Fanout Buffer
®
8T49N028
DATA SHEET
General Description
The 8T49N028 is a low RMS phase jitter Clock Synthesizer with
selectable internal crystal oscillator or external clock references and
eight outputs, configurable as either LVDS, LVPECL or High
Impedance.
After power up, two frequency select pins determine one of up to four
different sets of factory preprogrammed crystal or input frequency
and output frequency configurations. From a single input reference,
as many as three different output frequencies may be selected for
the output banks: two of these frequencies can be generated by the
internal crystal oscillator, and/or external clock pre-divider, and/or A
output divider, and/or B output divider. The third output frequency is
from the B output divider. Device pre-programming can be
overwritten through the provided I
2
C interface.
Examples of valid frequency configuration setups illustrate this
device's flexibility, and are shown in Table 3A. The specific internal
register settings for each of the four frequency sets are specified by
an IDT order code. Custom codes can be provided by contacting
IDT.
Features
•
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Fourth Generation FemtoClock NG PLL technology
Eight selectable LVPECL or LVDS outputs (bank selectable, two
output channels per bank)
CLK, nCLK input pair can accept the following differential input
levels: LVPECL, LVDS, HCSL
FemtoClock NG VCO Range: 1.92GHz - 2.5GHz
Bank A and B output frequencies are mux selectable from internal
crystal oscillator, reference clock input, output divider A or output
divider B
Clock from OUTPUT DIVIDER A, RMS phase jitter at 156.25MHz
(12KHz - 20MHz): 225fs (typical)
Clock from OUTPUT DIVIDER B, RMS phase jitter at 156.25MHz
(12KHz - 20MHz): 219fs (typical)
Clock from OUTPUT DIVIDER B, RMS phase jitter at 156.25MHz
(10kHz - 1MHz): 165fs (typical) Full 2.5V or 3.3V power supply
Full 2.5V or 3.3V power supply
I
2
C programming interface
PCI Express (2.5 Gb/S), Gen 2 (5 Gb/s) and Gen 3 (8 Gb/s) jitter
compliant
-40°C to 85°C ambient operating temperature
Lead-free (RoHS 6) packaging
Pin Assignment
CLK_SEL
SDATA
LOCK
SCLK
nCLK
V
CCA
CLK
V
EE
V
EE
V
EE
nc
Q0
nQ0
Q1
nQ1
V
CCO_A
nc
nc
V
CCO_B
Q2
nQ2
Q3
nQ3
48 47 46 45 44 43 42 41 40 39 38 37
36
1
2
3
4
5
6
7
8
9
10
11
35
34
33
32
nc
V
EE
Q4
nQ4
Q5
nQ5
V
CCO_C
V
CCO_D
Q6
nQ6
Q7
nQ7
V
EE
31
30
29
28
27
26
8T49N028
25
12
13 14 15 16 17 18 19 20 21 22 23 24
nc
FSEL0
XTAL_OUT
FSEL1
V
EE
V
EE
V
EE
ADDR_SEL
XTAL_IN
V
CC
48-pin, 7mm x 7mm VFQFN Package
8T49N028 REVISION 1 10/16/14
1
©2014 Integrated Device Technology, Inc.
V
CC
V
EE
8T49N028 DATA SHEET
Pin Description and Pin Characteristic Tables
Table 1. Pin Descriptions
Number
1, 2
3, 4
5
6, 7,
14, 37, 40
8
9, 10
11, 12
13, 17, 21,
24, 25, 36,
41, 44, 48
15,
16
18, 22
Name
Q0, nQ0
Q1, nQ1
V
CCO_A
nc
V
CCO_B
Q2, nQ2
Q3, nQ3
V
EE
ePAD
XTAL_IN
XTAL_OUT
V
CC
Output
Output
Power
Unused
Power
Output
Output
Power
Type
Description
Differential output pair. LVPECL or LVDS interface levels. (Bank A)
Differential output pair. LVPECL or LVDS interface levels. (Bank A)
Output supply pins for Bank A
No connect.
Output supply pins for Bank B
Differential output pair. LVPECL or LVDS interface levels. (Bank B)
Differential output pair. LVPECL or LVDS interface levels. (Bank B)
Negative supply pins. The Thermal Pad must be connected to V
EE
.
Crystal oscillator interface. XTAL_IN is the input, XTAL_OUT is the output.
Core supply pins.
Frequency and configuration. Selects between one of four factory
programmable power-up default configurations. The four configurations can
have different PLL states, output frequencies, output styles, multiplexer states
and output states. These default configurations can be overwritten after
power-up via I
2
C. LVCMOS/LVTTL interface levels.
00 = Configuration 0 (default)
01 = Configuration 1
10 = Configuration 2
11 = Configuration 3
I
2
C Address select pin. LVCMOS/LVTTL interface levels.
Differential output pair. LVPECL or LVDS interface levels. (Bank D)
Differential output pair. LVPECL or LVDS interface levels. (Bank D)
Output supply pins for Bank D.
Output supply pins for Bank C.
Differential output pair. LVPECL or LVDS interface levels. (Bank C)
Differential output pair. LVPECL or LVDS interface levels. (Bank C)
Pullup
Pullup
I
2
C Clock Input. LVCMOS/LVTTL interface levels.
I
2
C Data Input. Input: LVCMOS/LVTTL interface levels. Output: Open Drain.
Analog supply pin.
PLL Lock Indicator. LVCMOS/LVTTL interface levels.
Pullup /
Pulldown
Pulldown
Pulldown
Inverting differential clock input. Internal resistor bias to V
CC
/2.
Non-inverting differential clock input.
Input source control pin. LVCMOS/LVTTL interface levels.
0 = XTAL (default)
1 = CLK, nCLK
Input
Power
19,
23
FSEL0,
FSEL1
Input
Pulldown
20
26, 27
28, 29
30
31
32, 33
34, 35
38
39
42
43
45
46
47
ADDR_SEL
nQ7, Q7
nQ6, Q6
V
CCO_D
V
CCO_C
nQ5, Q5
nQ4, Q4
SCLK
SDATA
V
CCA
LOCK
nCLK
CLK
CLK_SEL
Input
Output
Output
Power
Power
Output
Output
Input
Input/Output
Power
Output
Input
Input
Input
Pulldown
NOTE:
Pullup
and
Pulldown
refer to internal input resistors. See Table 2,
Pin Characteristics,
for typical values.
REVISION 1 10/16/14
3
FEMTOCLOCK
®
NG CRYSTAL-TO-3.3V, 2.5V MULTIPLE FREQUENCY
CLOCK GENERATOR W/FANOUT BUFFER
京公网安备 11010802033920号
EEWORLD
